Invention Grant
- Patent Title: Method of forming well regions for field effect transistors utilizing self-aligned techniques
- Patent Title (中): 使用自对准技术形成场效应晶体管的区域的方法
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Application No.: US850037Application Date: 1986-04-10
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Publication No.: US4851364APublication Date: 1989-07-25
- Inventor: Yuji Yatsuda , Takaaki Hagiwara , Ryuji Kondo , Shinichi Minami , Yokichi Itoh
- Applicant: Yuji Yatsuda , Takaaki Hagiwara , Ryuji Kondo , Shinichi Minami , Yokichi Itoh
- Applicant Address: JPX Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JPX Tokyo
- Priority: JPX54-63941 19790525
- Main IPC: H01L27/112
- IPC: H01L27/112 ; G11C11/34 ; G11C14/00 ; G11C16/04 ; H01L21/76 ; H01L21/8246 ; H01L21/8247 ; H01L27/10 ; H01L27/105 ; H01L27/115 ; H01L29/78 ; H01L29/788 ; H01L29/792
Abstract:
The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.
Public/Granted literature
- US6131182A Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros Public/Granted day:2000-10-10
Information query
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