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23 条记录 (耗时 0.025 秒)

    Nonvolatile semiconductor memory
    5.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US4654828A

    公开(公告)日：1987-03-31

    申请号：US787021

    申请日：1985-10-15

    申请人： Takaaki Hagiwara ,  Yokichi Itoh ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    发明人： Takaaki Hagiwara ,  Yokichi Itoh ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/417 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L27/02 ,  H01L29/34 ,  H01L29/78

    CPC分类号： H01L27/105 ,  G11C16/0466 ,  H01L29/792 ,  Y10S257/903

    摘要： A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal-silicon nitride-silicon dioxide-semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal-silicon dioxide-semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

    摘要翻译： 一种半导体非易失性存储器，其中单元由由栅电极由多晶硅制成的MNOS（金属 - 氮化硅 - 二氧化硅 - 半导体）晶体管和MOS（金属 - 二氧化硅 - 半导体）晶体管）构成的串联连接构成， 其栅极也由多晶硅制成，这样的单电池以矩阵的形式排列，其中MOS晶体管的栅极用作读取字线，MNOS晶体管的栅电极用作 写入字线，并且串联连接并构成单元的MNOS晶体管和MOS晶体管中的任一个的端子被用作数据线。

    Semiconductor device having aligned semiconductor regions and a plurality of MISFETs
    7.
    发明授权
    Semiconductor device having aligned semiconductor regions and a plurality of MISFETs 失效
    半导体器件具有对准的半导体区域和多个MISFET

    公开(公告)号：US5519244A

    公开(公告)日：1996-05-21

    申请号：US268569

    申请日：1994-07-06

    申请人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Ryuji Kondo ,  Shinichi Minami ,  Yokichi Itoh

    发明人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Ryuji Kondo ,  Shinichi Minami ,  Yokichi Itoh

    IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/105

    CPC分类号： H01L27/105 ,  G11C16/0466

    摘要： The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

    摘要翻译： 本发明涉及一种半导体存储器电路器件，其中在半导体衬底的主表面上形成由半导体非易失性存储元件组成的矩形存储器阵列部分，形成低电压驱动电路（解码器） 沿着存储器阵列部分的一侧，并且沿着存储器阵列部分的相对侧形成高压驱动电路。 这允许字线长度减小并且避免字线的交叉以允许增加的操作速度，特别是增加的读取速度。

    Semiconductor device and method for manufacturing the same
    8.
    发明授权
    Semiconductor device and method for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US5348898A

    公开(公告)日：1994-09-20

    申请号：US9061

    申请日：1993-01-26

    申请人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Ryuji Kondo ,  Shinichi Minami ,  Yokichi Itoh

    发明人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Ryuji Kondo ,  Shinichi Minami ,  Yokichi Itoh

    IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/105 ,  H01L21/265

    CPC分类号： H01L27/105 ,  G11C16/0466

    摘要： The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

    摘要翻译： 本发明涉及一种半导体存储器电路器件，其中在半导体衬底的主表面上形成由半导体非易失性存储元件组成的矩形存储器阵列部分，形成低电压驱动电路（解码器） 沿着存储器阵列部分的一侧，并且沿着存储器阵列部分的相对侧形成高压驱动电路。 这允许字线长度减小并且避免字线的交叉以允许增加的操作速度，特别是增加的读取速度。

    Nonvolatile MNOS semiconductor memory
    9.
    发明授权
    Nonvolatile MNOS semiconductor memory 失效
    非易失性MNOS半导体存储器

    公开(公告)号：US4460980A

    公开(公告)日：1984-07-17

    申请号：US193124

    申请日：1980-10-02

    申请人： Takaaki Hagiwara ,  Yokichi Itoh ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    发明人： Takaaki Hagiwara ,  Yokichi Itoh ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/417 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L27/02 ,  H01L29/34 ,  H01L29/78

    CPC分类号： H01L27/105 ,  G11C16/0466 ,  H01L29/792 ,  Y10S257/903

    摘要： A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal--silicon nitride--silicon dioxide--semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal--silicon dioxide--semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

    摘要翻译： 一种半导体非易失性存储器，其中单元由由栅电极由多晶硅制成的MNOS（金属 - 氮化硅 - 二氧化硅 - 半导体）晶体管和MOS（金属 - 二氧化硅 - 半导体）晶体管）构成的串联连接构成， 其栅极也由多晶硅制成，这样的单电池以矩阵的形式排列，其中MOS晶体管的栅极用作读取字线，MNOS晶体管的栅电极用作 写入字线，并且串联连接并构成单元的MNOS晶体管和MOS晶体管中的任一个的端子被用作数据线。

    Defect-remediable semiconductor integrated circuit memory and spare substitution method in the same
    10.
    发明授权
    Defect-remediable semiconductor integrated circuit memory and spare substitution method in the same 失效
    缺陷补救半导体集成电路存储器和备用替代方法相同

    公开(公告)号：US4514830A

    公开(公告)日：1985-04-30

    申请号：US344974

    申请日：1982-02-02

    申请人： Takaaki Hagiwara ,  Masatada Horiuchi ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    发明人： Takaaki Hagiwara ,  Masatada Horiuchi ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    IPC分类号： H01L27/112 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC分类号： G11C29/789

    摘要： An LSI memory comprises a memory array including usual memory cells arranged in a matrix form, usual address transistors for selecting usual lines connected to the columns or rows of the memory array, address lines for controlling the usual address transistors, spare memory cells provided in the memory array, a spare line connected to the spare memory cells, spare address transistors connected between the address lines and the spare lines, and nonvolatile memory elements connected between the sources of the spare address transistors and the ground. By putting any one of the nonvolatile memory elements into the written state, any one of the spare address transistors are conditioned into an active state so that the spare line can be substituted for a defective usual line.

    摘要翻译： LSI存储器包括存储器阵列，其包括以矩阵形式布置的常规存储器单元，用于选择连接到存储器阵列的列或行的常用线的常用地址晶体管，用于控制通常地址晶体管的地址线，设置在存储器阵列中的备用存储器单元 存储器阵列，连接到备用存储器单元的备用线路，连接在地址线和备用线路之间的备用地址晶体管，以及连接在备用地址晶体管的源极和地之间的非易失性存储器元件。 通过将非易失性存储器元件中的任何一个置于写入状态，任何一个备用地址晶体管被调节成活动状态，使得备用线可以代替缺陷通常的线。