发明授权
- 专利标题: Fabrication method for semiconductor integrated circuits
- 专利标题(中): 半导体集成电路的制造方法
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申请号: US245297申请日: 1988-09-16
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公开(公告)号: US4866000A公开(公告)日: 1989-09-12
- 发明人: Yoshihisa Okita
- 申请人: Yoshihisa Okita
- 申请人地址: JPX Tokyo
- 专利权人: Oki Electric Industry Co., Ltd.
- 当前专利权人: Oki Electric Industry Co., Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX62-229746 19870916
- 主分类号: H01L29/73
- IPC分类号: H01L29/73 ; H01L21/285 ; H01L21/331 ; H01L29/732
摘要:
In method of fabricating a bipolar transistor on a semiconductor substrate, the emitter pattern is formed using the horizontal etching effect and filling-in effect of the RF-bias sputtering method, so a fine, self-aligned emitter pattern can be created that is disposed entirely in the center of the active base region without the use of photoetching. In addition, the passive base layer and the emitter layer can approach each other to any desired degree as long as they do not touch, so no high-concentration base layer is necessary, the base resistance is reduced, and the passive base region is reduced to a very small size. Furthermore, after the formation of the base region, the only heat treatment step that alters the diffusion layer profile is the formation of the emitter layer, so the use of a thin epitaxial layer to reduce the collector resistance does not result in proximity of the buried collector layer and the passive base layer.
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