发明授权
US4893269A Adder cell for carry-save arithmetic 失效
加法单元进行保存算术

Adder cell for carry-save arithmetic
摘要:
An adder cell in which the sum signal and the carry signal are formed with equal speed is provided for employment in "carry-save" adders, wherein the sum signal and the carry signal are separately forwarded to separate inputs of following adder cells. The circuit of the adder cell is designed such that the sum signal as well as the carry signal each have to traverse only two gates, so that the running times of sum signal and carry signal are approximately identical and shorter than the maximum running time of conventional adder cells.
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