公开(公告)号：US4893269A

公开(公告)日：1990-01-09

申请号：US324807

申请日：1989-03-17

申请人： Karl Knauer ,  Winfried Kamp

发明人： Karl Knauer ,  Winfried Kamp

IPC分类号： G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/508

CPC分类号： G06F7/501

摘要： An adder cell in which the sum signal and the carry signal are formed with equal speed is provided for employment in "carry-save" adders, wherein the sum signal and the carry signal are separately forwarded to separate inputs of following adder cells. The circuit of the adder cell is designed such that the sum signal as well as the carry signal each have to traverse only two gates, so that the running times of sum signal and carry signal are approximately identical and shorter than the maximum running time of conventional adder cells.

摘要翻译： 在“进位保存”加法器中提供加和信号和进位信号以相等速度形成的加法器单元，其中和信号和进位信号分别转发到后续加法器单元的分离输入。 加法器单元的电路被设计成使得和信号以及进位信号各自必须仅穿过两个门，使得和信号和进位信号的运行时间大致相同并且短于常规的最大运行时间 加法器单元。

公开(公告)号：US5027312A

公开(公告)日：1991-06-25

申请号：US380601

申请日：1989-07-17

申请人： Karl Knauer ,  Winfried Kamp

发明人： Karl Knauer ,  Winfried Kamp

IPC分类号： G06F7/50 ,  G06F7/506 ,  G06F7/507 ,  G06F7/508

CPC分类号： G06F7/507 ,  G06F2207/3876

摘要： A carry-select adder composed of blocks, each containing an input adder cell and a number of adder cells of a first and second type. Each block has one input adder cell interconnected to adder cells of the first and second type which are connected in an alternating fashion. The cells are connected to each other via carry lines and block carry lines. The adder cells of the first and second type each have a gate arrangement which utilizes field effect transistors for transfer, pull-up and pull-down transistors. These transistors are not a component part of a combination gate within an adder cell. The gate arrangement significantly increases the processing speed of the carry-select adder.

摘要翻译： 由块组成的进位选择加法器，每个都包含输入加法器单元和第一和第二类型的加法器单元的数量。 每个块具有互连到第一和第二类型的加法器单元的一个输入加法器单元，以交替方式连接。 单元通过输送线和块输送线相互连接。 第一和第二类型的加法器单元各自具有栅极布置，其利用用于传输，上拉和下拉晶体管的场效应晶体管。 这些晶体管不是加法器单元内的组合门的组成部分。 门排列显着增加了进位选择加法器的处理速度。

公开(公告)号：US5479107A

公开(公告)日：1995-12-26

申请号：US331576

申请日：1994-11-02

申请人： Karl Knauer

发明人： Karl Knauer

IPC分类号： H03K19/096 ,  H03K19/01 ,  H03K19/0948

CPC分类号： H03K19/0963

摘要： An asynchronous logic circuit has a plurality of input lines (I) connected both to an n-channel logic block (NL) and to a p-channel logic block (PL) which is inverse with respect thereto (split transistor switch logic), in which, both in response to a rising and to a falling edge of a request signal at a request input (REQ), valid output data can be produced at outputs (OUT1, OUT2) of the asynchronous logic circuit in each case before a signal change at a ready-message output (RDY). Advantages are in particular the low outlay on circuitry and the doubling of the throughput in comparison with a corresponding status-controlled asynchronous logic circuit.

摘要翻译： PCT No.PCT / DE93 / 00380 Sec。 371日期：1994年11月2日 102（e）1994年11月2日日期PCT 1993年4月30日PCT PCT。 公开号WO93 / 22838 日期11月11日，1993.异步逻辑电路具有连接到n沟道逻辑块（NL）和与其相反的p沟道逻辑块（PL）的多个输入线（I） 分立晶体管开关逻辑），其中响应于请求输入（REQ）处的请求信号的上升沿和下降沿，可以在异步逻辑电路的输出（OUT1，OUT2）处产生有效的输出数据 在每种情况下，在即时消息输出（RDY）的信号变化之前。 与相应的状态控制的异步逻辑电路相比，优点尤其在电路上的低成本和吞吐量的翻倍。

公开(公告)号：US4142109A

公开(公告)日：1979-02-27

申请号：US641818

申请日：1975-12-17

申请人： Karl Knauer

发明人： Karl Knauer

IPC分类号： G11C19/28 ,  H01L29/768 ,  H01L29/66

CPC分类号： H01L29/76841 ,  G11C19/282

摘要： A buried channel charge coupled device (BCCD) is operated by an improved process in a two-phase operation. The device includes a buried channel in a semiconductor substrate below an insulating layer on a surface of the substrate and below the electrodes of the device. The electrodes are divided into first and second electrodes with the first electrodes spaced apart in a first level of the insulating layer and electrically insulated from the semiconductor substrate and the second electrodes spaced apart and carried by the insulating layer in a second level and arranged over the interspaces between the first electrodes. Each of the second electrodes is electrically connected to an adjacent first electrode. The device is operated in a two-phase manner and the operation is improved by the provision of a bias voltage which is connected either to all of the electrodes or to the substrate, the bias voltage effecting a potential difference between the electrodes and the substrate which is either greater than or less than a predetermined magnitude so as to effect charge shifting in one direction or the other, respectively.

摘要翻译： 掩埋通道电荷耦合器件（BCCD）通过两相操作中的改进工艺进行操作。 该器件包括在衬底的表面上的绝缘层下方的半导体衬底内的掩埋沟道，并且在器件的电极之下。 电极被分成第一和第二电极，其中第一电极在绝缘层的第一电平中间隔开并且与半导体衬底和第二电极电绝缘，并且绝缘层间隔开并承载在第二电平上并且布置在 第一电极之间的间隙。 每个第二电极电连接到相邻的第一电极。 器件以两相方式操作，并且通过提供连接到所有电极或衬底的偏置电压来改善操作，偏置电压影响电极和衬底之间的电位差， 大于或小于预定值，以分别实现一个方向上的电荷移动。

公开(公告)号：US5382844A

公开(公告)日：1995-01-17

申请号：US146061

申请日：1993-11-03

申请人： Karl Knauer

发明人： Karl Knauer

IPC分类号： H03K19/0948 ,  H03K19/00 ,  H03K19/096 ,  H03K19/173 ,  H03K19/20

CPC分类号： H03K19/1738 ,  H03K19/0013 ,  H03K19/0963

摘要： A logic circuit for asynchronous circuits, in which logic circuit signals which are present at the input (in) of the logic circuit can be linked both in a first logic block (NL) and also in a second logic block (PL) inverse thereto, and in which logic circuit, at a complete message output (cmpl), a signal can be formed to report valid data at an output (out) of the logic circuit, by a logic link (E), from signals from outputs of both logic blocks. In order to achieve a greater interference resistance and a lower power loss with the simultaneous use of conventional CMOS logic blocks, the first logic section is formed with n-channel transistors and the second logic section is formed with p-channel transistors and the outputs (A1 and A6) of the two logic sections are coupled to one another via transistors (8 and 10).

摘要翻译： PCT No.PCT / DE92 / 00366 Sec。 371日期：1993年11月3日 102（e）日期1993年11月3日PCT提交1992年5月5日PCT公布。 WO92 / 20156 PCT出版物 日期：1992年11月12日。用于异步电路的逻辑电路，其中存在于逻辑电路的输入端（in）的逻辑电路信号可以在第一逻辑块（NL）和第二逻辑块 块（PL），并且其中逻辑电路在完整的消息输出（cmpl）处，可以形成信号以通过逻辑链路（E）在逻辑电路的输出（out）处报告有效数据， 来自两个逻辑块的输出的信号。 为了通过同时使用常规CMOS逻辑块来实现更大的抗干扰性和更低的功率损耗，第一逻辑部分由n沟道晶体管形成，第二逻辑部分由p​​沟道晶体管和输出（ A1和A6）经由晶体管（8和10）彼此耦合。

公开(公告)号：US4839849A

公开(公告)日：1989-06-13

申请号：US902745

申请日：1986-09-02

申请人： Karl Knauer

发明人： Karl Knauer

IPC分类号： G06F7/501 ,  G06F7/50 ,  G06F7/506

CPC分类号： G06F7/501

摘要： An adder cell for a ripple-carry adder, suitable for use in an integrated circuit employing CMOS technology, has a gate arrangement for two input variables and a carry input signal, with outputs for sum and carry signals, in accordance with the signals presented to the inputs. The gate arrangement is arranged so that the charging of the capacitance of the carry output takes place from a supply voltage through two transistor gates, not contained in a combination gate, so that one of the transistor gates may be formed as a driving inverter separate from the time-critical carry-propogation path, and designed with significantly lower impedance than the other transistor gates. Alternatively, a single transistor gate is employed for charging the capacitance of the carry output directly form a supply voltage.

摘要翻译： 用于纹波进位加法器的加法器单元适用于采用CMOS技术的集成电路，具有用于两个输入变量的门装置和一个进位输入信号，其具有和和进位信号的输出，根据提供给 输入。 栅极布置被布置成使得进位输出的电容的充电通过不包含在组合栅极中的两个晶体管栅极的电源电压进行，使得晶体管栅极中的一个可以形成为与 时间关键的进位传播路径，并设计成具有比其他晶体管栅极低得多的阻抗。 或者，单个晶体管栅极用于对进位输出的电容直接形成电源电压。

公开(公告)号：US4539537A

公开(公告)日：1985-09-03

申请号：US499483

申请日：1983-05-31

申请人： Hans-Joerg Pfleiderer ,  Karl Knauer

发明人： Hans-Joerg Pfleiderer ,  Karl Knauer

IPC分类号： H03H15/02

CPC分类号： H03H15/023

摘要： A transversal filter with an analog shift register has a plurality of parallel inputs and a serial output at which a filtered signal appears. An object is to provide as simple as possible a realization of the n signal evaluators allocated to the n stages of the shift register. This is achieved by providing the n signal evaluators in a signal path proceeding from the input of the first stage over all n stages, and to evaluate according to evaluation factors b.sub.n through b.sub.1 which occur in the system functionH(z)=b.sub.o .multidot.(1+b.sub.1 z(1+b.sub.2 .multidot.z( . . . 1+b.sub.n .multidot.z)))describing the filtered signal, where z is the delay which the signal values respectively experience when traversing a stage of the shift register. The filter is employed as an analog filter in communication technology.

摘要翻译： 具有模拟移位寄存器的横向滤波器具有多个并行输入和串行输出，滤波信号出现在该串行输出端。 目的是尽可能简单地提供分配给移位寄存器的n个级的n个信号评估器的实现。 这通过在从n个阶段的第一阶段的输入开始的信号路径中提供n个信号评估器来实现，并且根据系统函数H（z）=框（1）中发生的评估因子bn至b1来评估 + b1z（1 + b2xz（。... 1 + bnxz））），其中z是信号值在穿过移位寄存器的阶段时分别经历的延迟。 该滤波器用作通信技术中的模拟滤波器。

公开(公告)号：US4188597A

公开(公告)日：1980-02-12

申请号：US832234

申请日：1977-09-12

申请人： Karl Knauer

发明人： Karl Knauer

IPC分类号： H01L29/768 ,  H03H15/02 ,  H03H7/28 ,  G11C27/00 ,  H01L29/78

CPC分类号： H03H15/02 ,  H01L29/76891 ,  H03H15/023

摘要： In an illustrated embodiment, at least one analog shift register has a number of parallel inputs and one series output. A number of individual evaluating circuits receive the signal to be filtered and supply respective output quantities of charge equal to the product of the difference between the relevant signal value and a predetermined minimum or maximum value, and a respective individual evaluation factor. The output of each evaluating circuit can be connected via a switching element to an associated parallel input. According to the present teaching, a considerably lesser space requirement is realized by operating the filter so that for every consecutive scanned value of the signal each evaluating circuit is read in twice consecutively with a charge shift between such read-in processes, no charge shift being effected between the second read-in process and the first read-in process for the next scanned signal value. Read-in of the held signal may be effected more than twice.

摘要翻译： 在所示实施例中，至少一个模拟移位寄存器具有多个并行输入和一个串联输出。 多个单独的评估电路接收要滤波的信号，并提供相应的输出电荷量等于相关信号值与预定最小值或最大值之差的乘积，以及各自的评估因子。 每个评估电路的输出可以经由开关元件连接到相关联的并行输入。 根据本教导，通过操作滤波器来实现相当小的空间要求，使得对于信号的每个连续的扫描值，每个评估电路在这种读入处理之间的电荷偏移连续两次读取，不将电荷移位 在第二读取过程和下一扫描信号值的第一读入过程之间进行。 保持信号的读入可能会进行两次以上。

公开(公告)号：US3987313A

公开(公告)日：1976-10-19

申请号：US537073

申请日：1974-12-30

申请人： Hans-Joerg Pfleiderer ,  Karl Knauer

发明人： Hans-Joerg Pfleiderer ,  Karl Knauer

IPC分类号： G11C27/04 ,  G06F1/04 ,  H03K3/037 ,  H03K5/15 ,  H03K5/151 ,  H03K23/80 ,  H03K21/00 ,  H04B1/00

CPC分类号： H03K5/15093 ,  H03K3/0372 ,  H03K5/1515

摘要： An arrangement for generating pulse trains for charged-coupled circuits employs a plurality of series-connected master-slave JK flip-flop circuits in which a Q output of a flip-flop circuit is connected to a J input of the following flip-flop circuit and in which a terminal for obtaining the generated timing pulses is provided at each Q output of a flip-flop circuit. A pulse train input for providing timing pulses to the flip-flop circuits and for each flip-flop circuit an NAND gate is provided whose output is connected to the clear input of the flip-flop circuit. One input of the NAND gate is connected to the timing pulse input line and another input is connected to a Q output of the following flip-flop circuit, except for the last flip-flop circuit in which the other input of the NAND gate associated therewith is connected to the Q output of the first flip-flop circuit. The K inputs of the flip-flop circuits are connected to a fixed potential, preferably a common connection to ground, and the individual flip-flop circuits may be additionally set by way of the clear inputs. In one embodiment the arrangement is constructed for two-phase operation and in another embodiment the arrangement is constructed for three-phase operation.

摘要翻译： 用于产生用于充电耦合电路的脉冲串的布置采用多个串联的主从JK触发器电路，其中触发电路的Q输出连接到以下触发器电路的J输入 并且其中在触发器电路的每个Q输出处提供用于获得产生的定时脉冲的端子。 提供用于向触发器电路和每个触发器电路提供定时脉冲的脉冲序列输入，其NAND输出与触发电路的清零输入相连。 与非门的一个输入端连接到定时脉冲输入线，另外一个输入连接到下面的触发器电路的Q输出，除了最后的触发器电路，其中与其相关联的与非门的另一个输入 连接到第一触发器电路的Q输出端。 触发器电路的K个输入端连接到固定电位，最好是连接到地的公共连接，并且各个触发电路可以通过清除输入额外设置。 在一个实施例中，该装置被构造用于两相操作，并且在另一实施例中，该装置被构造用于三相操作。

公开(公告)号：US5276773A

公开(公告)日：1994-01-04

申请号：US374745

申请日：1989-07-03

申请人： Karl Knauer ,  Ulrich Ramacher ,  Juergen Pandel ,  Hans-Joerg Pfleiderer

发明人： Karl Knauer ,  Ulrich Ramacher ,  Juergen Pandel ,  Hans-Joerg Pfleiderer

IPC分类号： G06F15/18 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00

CPC分类号： G06N3/063

摘要： A digital neural network has a plurality of neurons (NR) completely meshed with one another, each of which comprises an evaluation stage having a plurality of evaluators (B) that is equal in number to the plurality of neurons (NR) and each of which comprises a decision stage having a decision unit (E). An adjustment information (INF.sub.E) that effects a defined pre-adjustment of the decision unit (E) can be supplied to every decision unit (E) by a pre-processing means via an information input. A weighting information (INF.sub.G) can be supplied to every evaluator (B) by a pre-processing means via an individual information input. An output information (INF.sub.A) can be output by every decision unit (E) to a post-processing means via a respective individual information output. The information outputs of the decision units (E) are each connected to an individual processing input of all evaluators (B) allocated to the appertaining decision unit (E). Individual processing outputs of the evaluators (B) are connected to individual processing inputs of the decision unit (E) in the appertaining neuron (N), so that every output information (INF.sub.A) can be indirectly fed back onto every neuron (NR).

摘要翻译： 数字神经网络具有彼此完全啮合的多个神经元（NR），每个神经元（NR）包括评估阶段，其具有与多个神经元（NR）数目相等的多个评估器（B），其中每个 包括具有决定单元（E）的判定阶段。 可以通过预处理装置经由信息输入向每个判定单元（E）提供影响决定单元（E）的定义的预调整的调整信息（INFE）。 加密信息（INFG）可以通过预处理装置经由个人信息输入提供给每个评估者（B）。 输出信息（INFA）可以由每个决定单元（E）通过相应的个人信息输出输出到后处理装置。 决策单元（E）的信息输出各自连接到分配给独立决定单元（E）的所有评估者（B）的单独处理输入。 评估器（B）的单独处理输出连接到独立神经元（N）中的决策单元（E）的各个处理输入，使得每个输出信息（INFA）可被间接反馈到每个神经元（NR）。