发明授权
- 专利标题: Semiconductor integrated circuit with reduced power consumption
- 专利标题(中): 半导体集成电路降低功耗
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申请号: US190745申请日: 1988-05-05
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公开(公告)号: US4897560A公开(公告)日: 1990-01-30
- 发明人: Shinji Saito , Kazuyuki Nonaka , Hideji Sumi , Takehiro Akiyama
- 申请人: Shinji Saito , Kazuyuki Nonaka , Hideji Sumi , Takehiro Akiyama
- 申请人地址: JPX Kawasaki JPX Kasugai
- 专利权人: Fujitsu Limited,Fujitsu VLSI Limited
- 当前专利权人: Fujitsu Limited,Fujitsu VLSI Limited
- 当前专利权人地址: JPX Kawasaki JPX Kasugai
- 优先权: JPX62-112842 19870509
- 主分类号: H03L7/18
- IPC分类号: H03L7/18 ; H03J5/02 ; H03K3/2885 ; H03K17/00 ; H03K17/60 ; H03K19/00 ; H03K19/086
摘要:
A semiconductor integrated circuit includes a logic circuit which has first and second transistors constituting an emitter coupled transistor pair and a third transistor which is used as a constant current source, a bias circuit which includes a fourth transistor having an emitter from which a first predetermined voltage is supplied to a base of the third transistor and an impedance having one end coupled to a first power source and another end coupled to a base of the fourth transistor to supply a second predetermined voltage thereto, and a clamping circuit. The clamping circuit is OFF and does not perform a clamping operation with respect to the base of the fourth transistor when the entire semiconductor integrated circuit needs to operate. When the entire semiconductor integrated circuit does not need to operate, the clamping circuit is ON to clamp the base potential of the fourth transistor so as to reduce the power consumption of the semiconductor integrate circuit.
公开/授权文献
- US4383372A Instant position finder and course plotter 公开/授权日:1983-05-17
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