公开(公告)号：US4897560A

公开(公告)日：1990-01-30

申请号：US190745

申请日：1988-05-05

申请人： Shinji Saito ,  Kazuyuki Nonaka ,  Hideji Sumi ,  Takehiro Akiyama

发明人： Shinji Saito ,  Kazuyuki Nonaka ,  Hideji Sumi ,  Takehiro Akiyama

IPC分类号： H03L7/18 ,  H03J5/02 ,  H03K3/2885 ,  H03K17/00 ,  H03K17/60 ,  H03K19/00 ,  H03K19/086

CPC分类号： H03J5/0272 ,  H03K17/603 ,  H03K3/2885 ,  H03K2217/0036

摘要： A semiconductor integrated circuit includes a logic circuit which has first and second transistors constituting an emitter coupled transistor pair and a third transistor which is used as a constant current source, a bias circuit which includes a fourth transistor having an emitter from which a first predetermined voltage is supplied to a base of the third transistor and an impedance having one end coupled to a first power source and another end coupled to a base of the fourth transistor to supply a second predetermined voltage thereto, and a clamping circuit. The clamping circuit is OFF and does not perform a clamping operation with respect to the base of the fourth transistor when the entire semiconductor integrated circuit needs to operate. When the entire semiconductor integrated circuit does not need to operate, the clamping circuit is ON to clamp the base potential of the fourth transistor so as to reduce the power consumption of the semiconductor integrate circuit.

公开(公告)号：US5248909A

公开(公告)日：1993-09-28

申请号：US919371

申请日：1992-07-29

申请人： Kouju Aoki ,  Hideji Sumi ,  Moriaki Mizuno ,  Tetsuya Aisaka

发明人： Kouju Aoki ,  Hideji Sumi ,  Moriaki Mizuno ,  Tetsuya Aisaka

IPC分类号： H03K19/003 ,  H03K19/018

CPC分类号： H03K19/01812 ,  H03K19/00376

摘要： A level converting circuit converts a first signal which has an ECL level which is used in an ECL device into a second signal which has a GaAs logic level which is used in a GaAs device which is based on a GaAs substrate.

摘要翻译： 电平转换电路将具有ECL装置中使用的ECL电平的第一信号转换为具有基于GaAs衬底的GaAs器件中使用的GaAs逻辑电平的第二信号。

公开(公告)号：US4413300A

公开(公告)日：1983-11-01

申请号：US310974

申请日：1981-10-13

申请人： Hideji Sumi ,  Masayuki Kokado

发明人： Hideji Sumi ,  Masayuki Kokado

IPC分类号： H03F1/42 ,  H03F1/52 ,  H04L25/02 ,  H02H3/08

CPC分类号： H04L25/028 ,  H03F1/52

摘要： A line driver circuit having a protective circuit against excess currents, which includes a protective transistor for limiting the output current of an output-stage emitter-follower transistor. A detecting means for detecting the output current of the emitter-follower transistor and a pull-up transistor for pulling up the base potential of the protective transistor are provided. Before the output current becomes too large, the detecting means detects the output current to turn on the pull-up transistor. Then the base potential of the protective transistor is pulled up to turn on the protective transistor. As a result the base current of the emitter-follower transistor is decreased, so that the emitter-follower transistor is protected from being thermally destroyed.

摘要翻译： 一种具有防过电流保护电路的线路驱动器电路，其包括用于限制输出级射极跟随器晶体管的输出电流的保护晶体管。 提供一种用于检测射极跟随器晶体管的输出电流的检测装置和用于提升保护晶体管的基极电位的上拉晶体管。 在输出电流过大之前，检测装置检测输出电流以导通上拉晶体管。 然后将保护晶体管的基极电位上拉以导通保护晶体管。 结果，射极跟随器晶体管的基极电流减小，从而保护射极跟随器晶体管免受热破坏。

公开(公告)号：US5162676A

公开(公告)日：1992-11-10

申请号：US669987

申请日：1991-03-15

申请人： Kouju Aoki ,  Hideji Sumi ,  Moriaki Mizuno ,  Tetsuya Aisaka

发明人： Kouju Aoki ,  Hideji Sumi ,  Moriaki Mizuno ,  Tetsuya Aisaka

IPC分类号： H03K19/018 ,  H03K19/086

CPC分类号： H03K19/01812 ,  H03K19/086

摘要： A circuit has a level converting circuit for converting a signal having level in conformance with a first logic system into a signal having a level in conformance with a second logic system. The circuit includes first, second and third voltage lines for respectively supplying first, second and third power source voltages, a level converting circuit coupled to the first and third voltage lines for converting a first signal having a level in conformance with the first logic system into a second signal having a level in conformance with the second logic system, a reference voltage generating part coupled to the first and third voltage lines for generating a reference voltage based on at least the first power source voltage, so that the reference voltage undergoes a corresponding level deviation with respect to a level deviation of the second signal caused by a level deviation in the first signal which occurs due to a level deviation in the first power source voltage, and a logic circuit which employs the second logic system and is coupled to the second and third voltage lines for receiving the second signal from the level converting circuit and for outputting an output signal using the reference voltage from the reference voltage generating part as a bias signal. The first power source voltage is a positive voltage relative to the second power source voltage and the third power source voltage is a negative voltage relative to the second power source voltage.

公开(公告)号：US5130573A

公开(公告)日：1992-07-14

申请号：US616947

申请日：1990-11-21

申请人： Takanori Nawa ,  Naomi Mori ,  Hideji Sumi

发明人： Takanori Nawa ,  Naomi Mori ,  Hideji Sumi

IPC分类号： H03K19/086 ,  H03K19/018

CPC分类号： H03K19/01831 ,  H03K19/01812

摘要： A semiconductor integrated circuit includes an emitter-coupled logic circuit coupled between a first power source line and a second power source line. The emitter-coupled logic circuit has a differential circuit and an output buffer circuit. A wiring line is provided which is coupled to the emitter of a first transistor of the output buffer circuit and which carries an output signal of the emitter-coupled logic circuit to a circuit of the next stage. The semiconductor integrated circuit also includes a second transistor having an emitter coupled to the emitter of the first transistor, a collector coupled to the first power source line, and a base supplied with a second reference voltage, and a constant-current source coupled to the emitter of the first and second transistors and allowing a constant current to selectively pass through either the first transistor or the second transistor. A current switching circuit is formed by the first and second transistors and the constant-current source, and the constant current passes through either the first transistor or the second transistor on the basis of a potential of the base of the first transistor and the second reference voltage applied to the base of the second transistor.

公开(公告)号：US4437021A

公开(公告)日：1984-03-13

申请号：US309438

申请日：1981-10-07

申请人： Hideji Sumi ,  Masayuki Kokado

发明人： Hideji Sumi ,  Masayuki Kokado

IPC分类号： H04L25/02 ,  G06F3/00 ,  H03K5/02 ,  H03K17/04 ,  H03K3/33 ,  H03K3/01

CPC分类号： H03K5/02

摘要： A line driver circuit for driving a unit located a long distance away through a long transmission line, comprising an output stage having an emitter follower including transistors in which an output-stage transistor provides an output signal of a high potential or a low potential in response to the electric potential of an input signal. A discharge pass is connected to the base of the output-stage transistor, for drawing charges on the base of the output-stage transistor off thereof and thus shortening the fall time of the output waveform.

摘要翻译： 一种线驱动器电路，用于通过长传输线驱动长距离的单元，包括具有射极跟随器的输出级，所述射极跟随器包括晶体管，其中输出级晶体管提供响应中的高电位或低电位的输出信号 到输入信号的电位。 放电通道连接到输出级晶体管的基极，用于在其输出级晶体管的基极上抽取电荷，从而缩短输出波形的下降时间。