发明授权
- 专利标题: Semiconductor memory unit
- 专利标题(中): 半导体存储单元
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申请号: US228021申请日: 1988-08-04
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公开(公告)号: US4935898A公开(公告)日: 1990-06-19
- 发明人: Shuuichi Miyaoka , Masanori Odaka , Toshikazu Arai , Hiroshi Higuchi
- 申请人: Shuuichi Miyaoka , Masanori Odaka , Toshikazu Arai , Hiroshi Higuchi
- 申请人地址: JPX Tokyo JPX Tokyo JPX Akita
- 专利权人: Hitachi, Ltd.,Hitachi Microcomputer Engineering, Ltd.,Akita Electronics Co., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi Microcomputer Engineering, Ltd.,Akita Electronics Co., Ltd.
- 当前专利权人地址: JPX Tokyo JPX Tokyo JPX Akita
- 优先权: JPX62-249578 19871002
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C11/414 ; G11C11/418
摘要:
A semiconductor memory device having a plurality of memory arrays composed of mutually orthogonal row word lines and complementary column data lines, and static memory cells disposed in a lattice arrangement at the intersections of such word lines and complementary data lines; variable impedance load circuits having first P-channel MOSFETs disposed between the complementary data lines and a first supply voltage and kept normally in an on-state, and also having second P-channel MOSFETs connected in parallel with the first P-channel MOSFETs and cut off selectively in accordance with predetermined selection timing signals in a write mode; a plurality of signal generator circuits provided correspondingly to the memory arrays for forming the selection timing signals in accordance with write control signals and array selection signals, and then feeding the timing signals to the corresponding variable impedance load circuits; and a plurality of signal relay circuits provided correspondingly to a predetermined number of the signal generator circuits in such a manner that each signal relay circuit is disposed substantially at an intermediate position between the corresponding signal generator circuits, and transmitting to the corresponding signal generator circuits the write control signals obtained from the timing generator circuit TG. In this configuration, the signal transmitting paths between the timing generator circuit and the individual signal relay circuits are rendered mutually equivalent in length.