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    Semiconductor memory
    1.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US4899314A

    公开(公告)日：1990-02-06

    申请号：US184661

    申请日：1988-04-21

    申请人： Kazuhisa Miyamoto ,  Shuuichi Miyaoka ,  Masanori Odaka

    发明人： Kazuhisa Miyamoto ,  Shuuichi Miyaoka ,  Masanori Odaka

    IPC分类号： G11C11/414 ,  G11C5/14

    CPC分类号： G11C5/147

    摘要： A semiconductor integrated circuit is provided having first and second level generate circuits producing different levels and first and second emitter follower circuits respectively connected thereto. A level generated by one of the first and second level generate circuits is selectively supplied to either one of the first and second emitter follower circuits. This enables the first and second emitter follower circuits to supply the respective circuits formed in a semiconductor substrate with stable reference voltages.

    摘要翻译： 提供了具有产生不同电平的第一和第二电平发生电路以及分别与其连接的第一和第二射极跟随器电路的半导体集成电路。 由第一和第二电平发生电路之一产生的电平被选择性地提供给第一和第二射极跟随器电路中的任一个。 这使得第一和第二射极跟随器电路能够在半导体衬底中形成的各个电路提供稳定的参考电压。

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5512766A

    公开(公告)日：1996-04-30

    申请号：US137958

    申请日：1993-10-15

    申请人： Mitsugu Kusunoki ,  Shuuichi Miyaoka ,  Michiaki Nakayama ,  Kouji Kobayashi ,  Masato Ikeda ,  Takashi Ogata

    发明人： Mitsugu Kusunoki ,  Shuuichi Miyaoka ,  Michiaki Nakayama ,  Kouji Kobayashi ,  Masato Ikeda ,  Takashi Ogata

    IPC分类号： G11C11/412 ,  G11C5/02 ,  G11C11/40 ,  G11C11/401 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/177 ,  H01L27/02 ,  H01L27/10

    CPC分类号： G11C5/025 ,  H03K19/017527 ,  H03K19/17704 ,  Y10S257/906

    摘要： A logic block of a memory (LSI) with logic functions includes RAM macrocells (RAMO-RAM7) and a centrally located gate array (GAO-GA5). Clock pulse shaping circuits (CSPO, CSP1) and input/output portion (I/O) surround the logic block. The logic block power supply includes a smoothing capacitor (CC) that is substantially the same size as a cell (GC) of the gate array. Each RAM macrocell has memory mats (MATOO-MAT21), word lines (WO-W127), data lines (DO-D7), and peripheral circuits (MPCOO-MPC21), which includes an address decoder and a sense amp (SAO). An input unit cell (ICO) receives ECL level signals and outputs ECL level signals (FIG. 5 ) and MOS level signals (FIG. 6 ). The input unit cells and analogous output unit cells (OCO) are selectively used singly or in parallel to accommodate signals of different form and driving capability. A wiring line replacement region (LRP) connects memory macrocell wiring lines with logic block wiring lines. A sequence control circuit cell or aligner (ALNO, ALN1) contiguous to the RAM macrocells transmits output signals to the logic block on the wiring lines. A clock signal distribution circuit (CDA) is arranged centrally of the RAM macrocells for distributing ECL level clock signals. The clock signal distribution circuit includes clock switch amplifier circuits (CSAO-CSA9) including bipolar transistors and MOSFETs (FIG. 23 ).

    摘要翻译： 具有逻辑功能的存储器（LSI）的逻辑块包括RAM宏单元（RAMO-RAM7）和位于中心的门阵列（GAO-GA5）。 时钟脉冲整形电路（CSPO，CSP1）和输入/输出部分（I / O）围绕逻辑块。 逻辑块电源包括与门阵列的单元（GC）基本相同的尺寸的平滑电容器（CC）。 每个RAM宏单元具有包括地址解码器和读出放大器（SAO）的存储器垫（MATOO-MAT21），字线（WO-W127），数据线（_DO-_D7）和外围电路（MPCOO-MPC21）。 输入单元单元（ICO）接收ECL电平信号并输出​​ECL电平信号（图5）和MOS电平信号（图6）。 输入单元单元和类似输出单元单元（OCO）可以单独或并行选择性地使用，以适应不同形式和驱动能力的信号。 布线更换区域（LRP）将存储器宏单元布线与逻辑块布线相连。 与RAM宏单元相邻的序列控制电路单元或对准器（ALNO，ALN1）将输出信号发送到布线上的逻辑块。 时钟信号分配电路（CDA）被布置在RAM宏单元的中央以分配ECL电平时钟信号。 时钟信号分配电路包括包括双极晶体管和MOSFET的时钟转换放大器电路（CSAO-CSA9）（图23）。

    Semiconductor memory
    4.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5047986A

    公开(公告)日：1991-09-10

    申请号：US472637

    申请日：1990-01-30

    申请人： Kazuhisa Miyamoto ,  Shuuichi Miyaoka ,  Masanori Odaka

    发明人： Kazuhisa Miyamoto ,  Shuuichi Miyaoka ,  Masanori Odaka

    IPC分类号： G11C11/414 ,  G11C5/14

    CPC分类号： G11C5/147

    摘要： A semiconductor integrated circuit is provided having first and second level generate circuits producing different levels and first and second emitter follower circuits respectively connected thereto. A level generated by one of the first and second level generate circuits is selectively supplied to either one of the first and second emitter follower circuits. This enables the first and second emitter follower circuits to supply the respective circuits formed in a semiconductor substrate with stable reference voltages.

    Semiconductor memory device with dual selection circuitry including CMOS and bipolar transistors
    5.
    发明授权
    Semiconductor memory device with dual selection circuitry including CMOS and bipolar transistors 失效
    具有包括CMOS和双极晶体管的双选择电路的半导体存储器件

    公开(公告)号：US4961164A

    公开(公告)日：1990-10-02

    申请号：US430907

    申请日：1989-10-31

    申请人： Shuuichi Miyaoka ,  Masanori Odaka ,  Hiroshi Higuchi ,  Toshikazu Arai

    发明人： Shuuichi Miyaoka ,  Masanori Odaka ,  Hiroshi Higuchi ,  Toshikazu Arai

    IPC分类号： G11C11/41 ,  G11C8/10 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407

    CPC分类号： G11C8/10 ,  G11C8/14

    摘要： A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

    摘要翻译： 提供一种半导体存储器件，其包括多个存储器阵列，每个存储器阵列包括主字线，连接有多个存储器单元的子字线，以及选择性地将子字线连接到主字线的解码器。 主字线相对较短，因为它们在存储器阵列之间是电隔离的，因此它们的电阻可以相对较低。 主字线不与多个存储单元直接连接，这导致与通常情况下的主字线相比较较小的电容。 因此，半导体存储器件可以具有增强的操作速度。

    Semiconductor memory unit
    6.
    发明授权
    Semiconductor memory unit 失效
    半导体存储单元

    公开(公告)号：US4935898A

    公开(公告)日：1990-06-19

    申请号：US228021

    申请日：1988-08-04

    申请人： Shuuichi Miyaoka ,  Masanori Odaka ,  Toshikazu Arai ,  Hiroshi Higuchi

    发明人： Shuuichi Miyaoka ,  Masanori Odaka ,  Toshikazu Arai ,  Hiroshi Higuchi

    IPC分类号： G11C11/41 ,  G11C11/414 ,  G11C11/418

    CPC分类号： G11C11/418

    摘要： A semiconductor memory device having a plurality of memory arrays composed of mutually orthogonal row word lines and complementary column data lines, and static memory cells disposed in a lattice arrangement at the intersections of such word lines and complementary data lines; variable impedance load circuits having first P-channel MOSFETs disposed between the complementary data lines and a first supply voltage and kept normally in an on-state, and also having second P-channel MOSFETs connected in parallel with the first P-channel MOSFETs and cut off selectively in accordance with predetermined selection timing signals in a write mode; a plurality of signal generator circuits provided correspondingly to the memory arrays for forming the selection timing signals in accordance with write control signals and array selection signals, and then feeding the timing signals to the corresponding variable impedance load circuits; and a plurality of signal relay circuits provided correspondingly to a predetermined number of the signal generator circuits in such a manner that each signal relay circuit is disposed substantially at an intermediate position between the corresponding signal generator circuits, and transmitting to the corresponding signal generator circuits the write control signals obtained from the timing generator circuit TG. In this configuration, the signal transmitting paths between the timing generator circuit and the individual signal relay circuits are rendered mutually equivalent in length.

    摘要翻译： 一种半导体存储器件，具有由相互正交的行字线和互补列数据线构成的多个存储器阵列，以及以这种字线和互补数据线的交叉处的格子排列设置的静态存储单元; 可变阻抗负载电路具有设置在互补数据线之间的第一P沟道MOSFET和第一电源电压并且保持正常导通状态，并且还具有与第一P沟道MOSFET并联连接的第二P沟道MOSFET并切断 根据写入模式中的预定选择定时信号选择性地断开; 多个信号发生器电路，与存储器阵列相对应地设置，用于根据写入控制信号和阵列选择信号形成选择定时信号，然后将定时信号馈送到相应的可变阻抗负载电路; 以及多个信号中继电路，其以预定数量的信号发生器电路相应地设置，使得每个信号中继电路基本上设置在相应的信号发生器电路之间的中间位置，并且向相应的信号发生器电路发送 从定时发生器电路TG获得的写入控制信号。 在这种配置中，定时发生器电路和各个信号继电器电路之间的信号传输路径的长度相互等同。

    Semiconductor integrated circuit with bipolar transistors and MOSFETs
    7.
    发明授权
    Semiconductor integrated circuit with bipolar transistors and MOSFETs 失效
    具有双极晶体管和MOSFET的半导体集成电路

    公开(公告)号：US5220187A

    公开(公告)日：1993-06-15

    申请号：US917907

    申请日：1992-07-21

    申请人： Shuuichi Miyaoka ,  Masanori Odaka ,  Katsumi Ogiue

    发明人： Shuuichi Miyaoka ,  Masanori Odaka ,  Katsumi Ogiue

    IPC分类号： H01L21/82 ,  H01L27/118 ,  H03K19/0944 ,  H03K19/173

    CPC分类号： H03K19/09448 ,  H01L27/11896

    摘要： A logic circuit to be formed in a gate array is selected depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermined value, and a second Bi-CMOS circuit including an output bipolar transistor whose emitter size is larger than the emitter size of the output bipolar transistor of the first Bi-CMOS circuit. That is, the logic circuit is brought into a circuit form whose output load capacitance can be charged and discharged fastest. As a result, the logic circuit constructed in the gate array by adopting such a design technique has its operating speed raised. An improved structure is also provided for reducing wiring lengths by arranging bipolar transistors in adjacent basic cells to have mirror symmetry with one another. Further, particular gate width relationships are provided between MOSFETs within basic cells for reducing propagation delay and the required occupation area.

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5140550A

    公开(公告)日：1992-08-18

    申请号：US591883

    申请日：1990-10-02

    申请人： Shuuichi Miyaoka ,  Masanori Odaka ,  Hiroshi Higuchi ,  Toshikazu Arai

    发明人： Shuuichi Miyaoka ,  Masanori Odaka ,  Hiroshi Higuchi ,  Toshikazu Arai

    IPC分类号： G11C8/10 ,  G11C8/14

    CPC分类号： G11C8/10 ,  G11C8/14

    摘要： A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

    摘要翻译： 提供一种半导体存储器件，其包括多个存储器阵列，每个存储器阵列包括主字线，连接有多个存储器单元的子字线，以及选择性地将子字线连接到主字线的解码器。 主字线相对较短，因为它们在存储器阵列之间是电隔离的，因此它们的电阻可以相对较低。 主字线不与多个存储单元直接连接，这导致与通常情况下的主字线相比较较小的电容。 因此，半导体存储器件可以具有增强的操作速度。