A non-volatile memory cell includes a MOS transistor of double gate construction. The MOS memory transistor includes a floating gate structure which includes electrically separated first and second segmented floating gates (4a; 4b). For the purpose of writing data, electrons are independently injected into the first and second segmented floating gates. Data are stored in the MOS memory transistor in three different non-volatile storage levels; one with electron accumulated either one of the two segmented floating gates; another with electrons injected into both of the segmented floating gates; and still another with no electrons accumulated on both of the segmented floating gates.