A semiconductor memory cell, and methods of fabricating same, that includes a substrate (10) and a plurality of trench capacitors (12) formed at least partially within the substrate and dielectrically isolated therefrom. A silicon-on-insulator (SOI) region includes a silicon layer (16) that overlies an insulator (14). The silicon layer is differentiated into a plurality of active device regions, each of which is disposed above one of the electrically conductive regions. Each of the active device regions is coupled to an overlying first electrode, or wordline (20), for forming a gate node of an access transistor (1), to a second electrode, or bitline (32), for forming a source node of the access transistor, and to the underlying trench capacitor for forming a drain node of the access transistor. The wordline includes a pair of opposed, electrically insulating vertical sidewalls, and the source node and the drain node of each of the access transistors are each comprised of an electrical conductor disposed upon one of the vertical sidewalls. The array of memory cells further includes structure (11, 13) for coupling the active device regions to the substrate to reduce or eliminate a floating substrate effect.