发明授权
US5096842A Method of fabricating bipolar transistor using self-aligned polysilicon
technology
失效
使用自对准多晶硅技术制造双极晶体管的方法
- 专利标题: Method of fabricating bipolar transistor using self-aligned polysilicon technology
- 专利标题(中): 使用自对准多晶硅技术制造双极晶体管的方法
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申请号: US350860申请日: 1989-05-09
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公开(公告)号: US5096842A公开(公告)日: 1992-03-17
- 发明人: Hiroyuki Nihira , Nobuyuki Itoh , Hiroomi Nakajima , Eiryo Tsukioka , Toshio Yamaguchi
- 申请人: Hiroyuki Nihira , Nobuyuki Itoh , Hiroomi Nakajima , Eiryo Tsukioka , Toshio Yamaguchi
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX63-118458 19880516; JPX63-172302 19880711; JPX63-207446 19880823
- 主分类号: H01L21/266
- IPC分类号: H01L21/266 ; H01L21/285 ; H01L21/308 ; H01L21/3105 ; H01L21/3213 ; H01L21/331 ; H01L29/08 ; H01L29/732
摘要:
In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an active base layer and a collector layer. When a polysilicon film pattern which defines an active base region and serves as a portion of a base electrode is formed on a wafer surface, a surface portion of a photoresist serving as an etching mask is converted to a carbonized layer by ion implantation. When a micronized emitter layer is formed by a polysilicon-emitter technology, ion implantation is performed before deposition of the polysilicon film or an impurity is doped in the polysilicon film simultaneously with deposition, and rapid thermal annealing is performed so as to activate the doped impurity.
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