A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate. The method of manufacturing the semiconductor memory includes a lapping process for lapping the surface of a wafer in forming the semiconductor regions in recesses formed by the insulating layer. The lapping process uses an alkaline liquid as a lapping liquid and employs a lapping disk provided with a hard lapping pad to finish the surfaces of the semiconductor regions flush with the surface of the insulating layer by lapping.