An integrated circuit comprises a first clock driver responsive to an external clock signal and producing a first clock signal, a second clock driver responsive to the first clock signal and producing a second clock signal delayed from the first clock signal, an internal circuit responsive to the second clock signal and producing an output data signal, and an output circuit coupled to a data output pin and transferring the output data signal to the data output pin in synchronization with the first clock signal, so that a time interval between the production of the output data signal and the validity at the data output pin is shrunk even though a large parasitic capacitance is coupled to the data output pin.