A test mode input detection circuit for a semiconductor device comprises a first circuit including a group of transistors and a load element, the transistors and load element being connected in series between a power source and an input terminal, a node between the transistor group and the load element forming an output terminal of the first circuit; a second circuit including a transistor whose gate receives an output from the output terminal of the first circuit, and a transistor whose gate receives a power source voltage, these transistors being connected in series between the power source and a ground, a node between the transistors forming an output terminal of the second circuit; and an inverter circuit for providing a test mode signal in response to an output of the second circuit.