公开(公告)号：US5428580A

公开(公告)日：1995-06-27

申请号：US176431

申请日：1994-01-03

申请人： Hiromi Kawashima ,  Takao Akaogi

发明人： Hiromi Kawashima ,  Takao Akaogi

IPC分类号： G11C16/02 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3445 ,  G11C16/30 ,  G11C16/3436 ,  G11C16/3459 ,  G11C5/143

摘要： The object of the present invention is to provide a nonvolatile memory wherein stored data can be properly read at power-on even if the memory is designed to achieve faster operating speeds by performing operations such as bit line charge-up by detecting an address signal change and the turning-on of the power. A nonvolatile semiconductor memory in which, after a write or an erase operation, a read operation for verification is performed by applying a voltage at a first verification level V2, which is lower than an applied voltage for a normal read operation, or a voltage at a second verification level V3, which is higher than the applied voltage V1, the nonvolatile semiconductor memory comprising: an address-transition-detection circuit 1; a supply voltage detection circuit 3 for generating an initialization transition signal at the rise of a supply voltage when the supply voltage has reached a first supply voltage transition threshold level V4 higher than the first verification level V2; and a transition operation circuit 2 for performing operations such as bit line charge-up in accordance with the address transition signal and initialization transition signal.

摘要翻译： 本发明的目的是提供一种非易失性存储器，其中存储的数据可以在上电时被适当地读取，即使存储器被设计为通过通过检测地址信号变化来执行诸如位线充电的操作来实现更快的操作速度 并开启电源。 一种非易失性半导体存储器，其中，在写入或擦除操作之后，通过施加低于正常读取操作的施加电压的第一验证电平V2或者正常读取操作的电压来执行用于验证的读取操作 第二验证电平V3高于施加的电压V1，非易失性半导体存储器包括：地址转换检测电路1; 电源电压检测电路3，用于当电源电压达到高于第一验证电平V2的第一电源电压转变阈值电平V4时，在电源电压上升时产生初始化转换信号; 以及用于根据地址转换信号和初始化转换信号执行诸如位线充电的操作的转换操作电路2。

公开(公告)号：US4773046A

公开(公告)日：1988-09-20

申请号：US60018

申请日：1987-06-09

申请人： Takao Akaogi ,  Hiromi Kawashima

发明人： Takao Akaogi ,  Hiromi Kawashima

IPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00 ,  G11C11/36

CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C17/18 ,  G11C29/835

摘要： A semiconductor device comprises a fuse circuit having first and second fuses for storing an information bit represented by blown or unblown states of the fuses. The device uses an information output circuit for providing an output signal having a first logic level when at least one of the fuses is blown and an output signal having a second logic level when both the fuses are unblown. A detecting circuit in the device detects which one of the fuses is unblown.

摘要翻译： 一种半导体器件包括具有第一和第二熔丝的熔丝电路，用于存储由保险丝的熔断状态或非吹制状态所表示的信息位。 当熔丝中的至少一个熔断时，该装置使用信息输出电路来提供具有第一逻辑电平的输出信号，并且当两个保险丝都未被吹出时，该装置具有具有第二逻辑电平的输出信号。 该装置中的检测电路检测哪个保险丝未被吹出。

公开(公告)号：US4644182A

公开(公告)日：1987-02-17

申请号：US796452

申请日：1985-11-08

申请人： Hiromi Kawashima ,  Hideki Arakawa

发明人： Hiromi Kawashima ,  Hideki Arakawa

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/12 ,  G11C16/32 ,  H01L27/10 ,  H03H11/26 ,  H03K5/13 ,  H03K17/56 ,  H03K17/687

CPC分类号： G11C5/145 ,  G11C16/12 ,  G11C16/32

摘要： A delay circuit including: a P-channel enhancement-type transistor (Q.sub.11), linked between an input terminal (IN) and an output terminal (OUT); a capacitor (C) connected to the gate of the transistor (Q.sub.11); a charging switch (SW.sub.1) for charging the capacitor (C); a discharging switch (SW.sub.2) for discharging the capacitor (C); and a control circuit (CONT) for controlling the charging switch (SW.sub.1) and the discharging switch (SW.sub.2). The delay time period is determined by the discharging operation of the discharging switch (SW.sub.1) after the charging operation of the charging switch (SW.sub.1).

摘要翻译： 一种延迟电路，包括：连接在输入端子（IN）和输出端子（OUT）之间的P沟道增强型晶体管（Q11）; 连接到晶体管（Q11）的栅极的电容器（C）; 用于对电容器（C）充电的充电开关（SW1）; 用于放电电容器（C）的放电开关（SW2）; 以及用于控制充电开关（SW1）和放电开关（SW2）的控制电路（CONT）。 延迟时间由充电开关（SW1）充电后的放电开关（SW1）的放电动作决定。

公开(公告)号：US06563738B2

公开(公告)日：2003-05-13

申请号：US10150017

申请日：2002-05-20

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C1604

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

公开(公告)号：US5608670A

公开(公告)日：1997-03-04

申请号：US436721

申请日：1995-05-08

申请人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/21

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H03K19/018521 ,  H03K19/215 ,  H03K3/356147 ,  H03K3/356165

摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

摘要翻译： 本发明涉及擦除闪存的改进。 本发明的目的是缩短擦除时间。 在预擦除写入期间，一次以多行单位选择字线或位线中的至少一个，并且数据被同时写入多个选择晶体管。

公开(公告)号：US5173876A

公开(公告)日：1992-12-22

申请号：US584673

申请日：1990-09-19

申请人： Hiromi Kawashima ,  Yoshinori Tsujimura

发明人： Hiromi Kawashima ,  Yoshinori Tsujimura

IPC分类号： G11C17/00 ,  G06F12/14 ,  G06F21/00 ,  G06F21/24 ,  G11C7/20 ,  G11C16/02 ,  G11C16/10 ,  G11C16/22 ,  G11C16/32

CPC分类号： G06F21/79 ,  G06F12/1433 ,  G11C16/10 ,  G11C16/22 ,  G11C16/32 ,  G11C16/3495 ,  G11C7/20

摘要： Where an electrically erasable and programmable non-volatile semiconductor memory element (EEPROM cell) for storing a setting and releasing of the software data protection has already been set in the logic state designating the software data protection setting state, and operation of setting the logical state designating the software data protection setting is not applied to the EEPROM cell even if the address and data for setting the software data protection is input. Further, where the logic state designating the releasing of the software data protection has been set in the electrically erasable and programmable non-volatile semiconductor memory element, the operation of setting the logical state designating the release of the software data protection is not set to the EEPROM cell, even if the address and the data for releasing the software data protection is input.

公开(公告)号：US4744058A

公开(公告)日：1988-05-10

申请号：US930399

申请日：1986-11-14

申请人： Hiromi Kawashima ,  Hideki Arakawa

发明人： Hiromi Kawashima ,  Hideki Arakawa

IPC分类号： G11C17/00 ,  G11C8/12 ,  G11C11/401 ,  G11C29/10 ,  G11C29/34 ,  G11C13/00

CPC分类号： G11C29/34 ,  G11C8/12

摘要： A semiconductor programmable memory device, especially an E.sup.2 PROM, in which a checkerboard pattern for testing the operation of the memory matrix is easily written. The E.sup.2 PROM is provided with a circuit which can select all of the word lines or every other word line at the same time, and which can simultaneously select all of the bit lines. This circuit reduces the number of steps required to write a checkerboard pattern in the memory matrix to only four, regardless of the memory size. Therefore, the process time to write the checkerboard pattern is reduced to approximately 40 m sec, which is equivalent to the time required to write four bytes in the memory matrix.

摘要翻译： 一种半导体可编程存储器件，特别是E2PROM，其中易于写入用于测试存储器矩阵的操作的棋盘图案。 E2PROM设置有可以同时选择所有字线或每个其他字线的电路，并且可同时选择所有位线。 该电路将存储器矩阵中的棋盘图形写入所需的步骤数量减少到只有四个，而与内存大小无关。 因此，将棋盘格图案的处理时间减少到大约40m秒，这等于在存储器矩阵中写入四个字节所需的时间。

公开(公告)号：US5815440A

公开(公告)日：1998-09-29

申请号：US822036

申请日：1997-03-24

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/5004 ,  G11C29/88

摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

摘要翻译： 半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元 字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。 此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。 第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任一个有缺陷时，选择在2n个字线之外准备的2k个字线的块。 因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

公开(公告)号：US5576637A

公开(公告)日：1996-11-19

申请号：US441460

申请日：1995-05-15

申请人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/21

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H03K19/018521 ,  H03K19/215 ,  H03K3/356147 ,  H03K3/356165

摘要： An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input. The gates of the second and fourth nMIS transistors and the second and fourth pMIS transistors are connected to one another and provided with a second input. The sources of the second and third nMIS transistors are connected to each other and provide the exclusive OR of the first and second inputs.

摘要翻译： 异或电路包括第一串联电路，其中第一pMIS晶体管的源极连接到正电压电源线。 第一pMIS晶体管的漏极经由第二nMIS晶体管连接到第一nMIS晶体管的漏极。 第一nMIS晶体管的源极经由第四nMIS晶体管连接到低压电源线。 第二串联电路具有通过第二pMIS晶体管连接到高压电源线的第三nMIS晶体管的漏极。 第三个nMIS晶体管的源极连接到第三个pMIS晶体管的源极。 第三个pMIS晶体管的漏极通过第四个pMIS晶体管连接到低压电源线。 第一和第三nMIS晶体管和第一和第三pMIS晶体管的栅极彼此连接并提供有第一输入。 第二和第四nMIS晶体管和第二和第四pMIS晶体管的栅极彼此连接并提供有第二输入。 第二和第三nMIS晶体管的源极彼此连接并提供第一和第二输入的异或。

公开(公告)号：US4601020A

公开(公告)日：1986-07-15

申请号：US566321

申请日：1983-12-28

申请人： Hideki Arakawa ,  Hiromi Kawashima

发明人： Hideki Arakawa ,  Hiromi Kawashima

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C16/32 ,  G11C11/40

CPC分类号： G11C16/30 ,  G11C16/32 ,  G11C5/145

摘要： An EEPROM utilizing a tunneling electron for writing and/or erasing, has charge pump circuits for pumping charge onto selected column and row lines up to a high voltage. In each of the charge pump circuits, a transistor is provided for intercepting clock pulses applied to a capacitor in each of the charge pump circuits connected to unselected column and row lines.

摘要翻译： 使用用于写入和/或擦除的隧道电子的EEPROM具有用于将电荷泵送到选定的列和行列直到高电压的电荷泵电路。 在每个电荷泵电路中，提供晶体管，用于截取连接到未选择的列和行线的每个电荷泵电路中施加到电容器的时钟脉冲。