发明授权
US5198381A Method of making an E.sup.2 PROM cell with improved tunneling properties
having two implant stages
失效
制造具有两个植入阶段的具有改进的隧道特性的E2PROM细胞的方法
- 专利标题： Method of making an E.sup.2 PROM cell with improved tunneling properties having two implant stages
- 专利标题（中）： 制造具有两个植入阶段的具有改进的隧道特性的E2PROM细胞的方法
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申请号： US758554申请日： 1991-09-12
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公开(公告)号： US5198381A公开(公告)日： 1993-03-30
- 发明人: Kuang-Yeh Chang , Subhash R. Nariani
- 申请人： Kuang-Yeh Chang , Subhash R. Nariani
- 申请人地址： CA San Jose
- 专利权人： VLSI Technology, Inc.
- 当前专利权人： VLSI Technology, Inc.
- 当前专利权人地址： CA San Jose
- 主分类号： H01L21/8247
- IPC分类号： H01L21/8247 ; H01L21/28 ; H01L27/115 ; H01L29/788 ; H01L29/792
摘要：
The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.