公开(公告)号：US5374833A

公开(公告)日：1994-12-20

申请号：US775085

申请日：1991-10-11

申请人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

发明人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

IPC分类号： H01L21/76 ,  H01L21/314 ,  H01L21/316 ,  H01L23/29 ,  H01L23/532 ,  H01L27/115 ,  H02L45/00

CPC分类号： H01L23/291 ,  H01L21/314 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002 ,  Y10S438/91 ,  Y10S438/958

摘要： The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.

摘要翻译： 本发明涉及一种集成电路，其包括用于中和在制造期间在各种介电层中发生的电荷的一个或多个非晶硅层。 非晶硅层包括悬挂硅键，其中和电荷，否则将导致隔离击穿，损害集成电路性能并增加制造成本。

公开(公告)号：US5328865A

公开(公告)日：1994-07-12

申请号：US11084

申请日：1993-01-29

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002

摘要： A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer; forming an anti-fuse layer over the base layer; patterning the anti-fuse layer to form an anti-fuse island; forming an insulating layer over the anti-fuse island; forming a via hole through the insulating layer to the anti-fuse island; forming a conductive connection layer over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.

摘要翻译： 一种制造抗熔丝结构的方法，其特征在于形成导电基层的步骤; 在基层上形成抗熔丝层; 图案化抗熔丝层以形成抗熔丝岛; 在反熔丝岛上形成绝缘层; 形成通过所述绝缘层到所述反熔丝岛的通孔; 在所述绝缘层上并在所述通孔内形成导电连接层; 以及图案化所述导电连接层以形成与所述反熔丝岛的导电接触。 优选地，抗熔丝岛包括非晶硅，其可任选地被钛 - 钨合金的薄层覆盖。

公开(公告)号：US5602056A

公开(公告)日：1997-02-11

申请号：US434528

申请日：1995-05-04

申请人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

发明人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L23/29 ,  H01L23/532 ,  H01L27/115 ,  H01L21/44

CPC分类号： H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/314 ,  H01L21/31612 ,  H01L23/291 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002

摘要： The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

摘要翻译： 本发明涉及用于制造具有多层金属化的MOS器件的MOS器件和方法。 根据优选实施例，内部钝化用于抑制来自内部源的器件劣化。 用于制造这种器件的优选器件和方法包括形成富含硅的一个或多个氧化物层以提供这种内部钝化并改善热载流子寿命。 用于制造具有多层金属化的MOS器件的优选方法包括改变PECVD氧化物膜的组成，并且在一些实施例中改变这种氧化物的位置和厚度。 在示例性优选实施例中，通过将组合物改变为富含氧化物的氧化物来修饰PECVD氧化物层。

公开(公告)号：US5492865A

公开(公告)日：1996-02-20

申请号：US314425

申请日：1994-09-28

申请人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

发明人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

IPC分类号： H01L21/76 ,  H01L21/314 ,  H01L21/316 ,  H01L23/29 ,  H01L23/532 ,  H01L27/115 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L23/291 ,  H01L21/314 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002 ,  Y10S438/91 ,  Y10S438/958

摘要： The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.

摘要翻译： 本发明涉及一种集成电路，其包括用于中和在制造期间在各种介电层中发生的电荷的一个或多个非晶硅层。 非晶硅层包括悬挂硅键，其中和电荷，否则将导致隔离击穿，损害集成电路性能并增加制造成本。

公开(公告)号：US5587332A

公开(公告)日：1996-12-24

申请号：US938727

申请日：1992-09-01

申请人： Kuang-Yeh Chang ,  Subhash R. Nariani ,  William J. Boardman

发明人： Kuang-Yeh Chang ,  Subhash R. Nariani ,  William J. Boardman

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： The present invention relates to a flash EEPROM cell using polysilicon-to-polysilicon hot electron emission to erase the memory contents of the cell. Exemplary embodiments include a side gate, a control gate, a floating gate and source and drain regions. Appropriate biasing of these gates and source and drain regions controls the electron population of the floating gate. The memory cells may be of either the double polysilicon or triple polysilicon variety. Peripheral transistors are formed from a last formed polysilicon layer to avoid degrading the peripheral transistors.

摘要翻译： 本发明涉及使用多晶硅 - 多晶硅热电子发射来擦除单元的存储器内容的快闪EEPROM单元。 示例性实施例包括侧栅极，控制栅极，浮置栅极和源极和漏极区域。 这些栅极和源极和漏极区域的适当偏置控制浮栅的电子群。 存储单元可以是双重多晶硅或三重多晶硅品种。 外围晶体管由最后形成的多晶硅层形成，以避免外围晶体管的劣化。

公开(公告)号：US5290734A

公开(公告)日：1994-03-01

申请号：US736162

申请日：1991-07-26

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L21/283 ,  H01L21/311

CPC分类号： H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, a conductive protective material, such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distributions for the anti-fuse structure and help prevent anti-fuse failure.

摘要翻译： 一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的衬底上的氧化物层，设置在开口内并接触衬底的非晶硅材料，设置在非晶态上的导电保护材料，例如钛钨 硅材料和衬在保护材料内形成的凹部的壁上的氧化物间隔物。 保护材料和间隔物为反熔丝结构提供更严格的编程电压分布，并有助于防止反熔丝故障。

公开(公告)号：US5198381A

公开(公告)日：1993-03-30

申请号：US758554

申请日：1991-09-12

申请人： Kuang-Yeh Chang ,  Subhash R. Nariani

发明人： Kuang-Yeh Chang ,  Subhash R. Nariani

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28273 ,  Y10S438/981

摘要： The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

摘要翻译： 本发明涉及一种用于制造具有改进的隧道面积的半导体存储器件，特别是E2PROM的半导体存储器件和方法，其中电子行进到浮栅。 隧道区域的特点是在E2PROM的使用寿命期间可以实现相对较多的编程和擦除循环。 隧道区域包括通过两个植入阶段制造的隧道门。 因为这两个阶段是彼此分开的，因此可以独立地优化每个植入阶段以改善隧道区域的性质。 此外，用于限定植入区域的窗口容易制造并且被设计成有利于植入区域的形成。 定义窗口的方法有助于轻松扩展用于推进世代技术的过程。

公开(公告)号：US5763937A

公开(公告)日：1998-06-09

申请号：US277090

申请日：1994-07-19

申请人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

发明人： Vivek Jain ,  Dipankar Pramanik ,  Subhash R. Nariani ,  Kuang-Yeh Chang

IPC分类号： H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L27/115 ,  H01L29/78 ,  H01L23/58

CPC分类号： H01L29/6659 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/314 ,  H01L21/31612 ,  H01L21/76801 ,  H01L23/291 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002

摘要： The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

摘要翻译： 本发明涉及用于制造具有多层金属化的MOS器件的MOS器件和方法。 根据优选实施例，内部钝化用于抑制来自内部源的器件劣化。 用于制造这种器件的优选器件和方法包括形成富含硅的一个或多个氧化物层以提供这种内部钝化并改善热载流子寿命。 用于制造具有多层金属化的MOS器件的优选方法包括改变PECVD氧化物膜的组成，并且在一些实施例中改变这种氧化物的位置和厚度。 在示例性优选实施例中，通过将组合物改变为富含氧化物的氧化物来修饰PECVD氧化物层。

公开(公告)号：US5371393A

公开(公告)日：1994-12-06

申请号：US221463

申请日：1994-04-01

申请人： Kuang-Yeh Chang ,  Subhash R. Nariani

发明人： Kuang-Yeh Chang ,  Subhash R. Nariani

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L21/28273 ,  Y10S438/981

摘要： The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

摘要翻译： 本发明涉及一种用于制造具有改进的隧道面积的半导体存储器件，特别是E2PROM的半导体存储器件和方法，其中电子行进到浮栅。 隧道区域的特点是在E2PROM的使用寿命期间可以实现相对较多的编程和擦除循环。 隧道区域包括通过两个植入阶段制造的隧道门。 因为这两个阶段是彼此分开的，因此可以独立地优化每个植入阶段以改善隧道区域的性质。 此外，用于限定植入区域的窗口容易制造并且被设计成有利于植入区域的形成。 定义窗口的方法有助于轻松扩展用于推进世代技术的过程。

公开(公告)号：US5120679A

公开(公告)日：1992-06-09

申请号：US710220

申请日：1991-06-04

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/82 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, and oxide spacers lining the walls of a recess formed within the amorphous silicon. The spacers prevent failures of the anti-fuse structures by covering cusps formed in the amorphous silicon material. The method of the present invention forms the above-described anti-fuse structure and further solves the problem of removing unwanted spacer material from areas outside of the anti-fuse structure locations.

摘要翻译： 一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的基底上的氧化物层，设置在开口内并接触基底的非晶硅材料以及衬在非晶硅内形成的凹陷壁的氧化物间隔物 。 间隔物通过覆盖形成在非晶硅材料中的尖头来防止抗熔丝结构的故障。 本发明的方法形成上述反熔丝结构，并且进一步解决了从抗熔丝结构位置之外的区域去除不想要的隔离材料的问题。