摘要:
An IC wafer containing thin oxide is fabricated to include at least two differentially-sized plate areas that may be upper plates of capacitors, or gates of associated MOS transistors. Before testing, the thin gate oxide underlying these plate areas is intentionally stressed by applying a stress current between these plates and the substrate. The stress current magnitude is scaled to the plate area such that each plate sees a substantially constant current density. Because weak oxide defects occur somewhat uniformly throughout the thin oxide, a larger plate or gate will overlie more weak oxide defects than will a plate or gate. If wafer test leakage current between the larger plate or gate and substrate exceeds leakage current between the smaller plate or gate and substrate, weak oxide is indicated because the defect is area dependent. By contrast, charge-induced damage is substantially independent of the areas of the plates or gates, due to the scaling of the stress-inducing currents. Thus, if test leakage current on the wafer is substantially the same for the large and small sized plates or gates, charge-damaged oxide is indicated because the damage is not area dependent. If desired, defects in the thin (gate) oxide may be identified by examining the characteristics of the test MOS devices. The gate-like plates (and if present associated MOS devices) are sufficiently small to be fabricated within scribe lines of the wafer to be tested.
摘要:
A method produces a capacitor. On a substrate, a first polysilicon layer is formed over an insulating region. A metal-silicide layer is formed on top of the first polysilicon layer. A dielectric layer is formed on top of the metal-silicide layer. A second polysilicon layer is formed on top of the dielectric layer. The second polysilicon layer and the dielectric layer are etched to form a top electrode and dielectric region. The metal-silicide layer and the first polysilicon layer are etched to form a bottom electrode.
摘要:
The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
摘要:
A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer; forming an anti-fuse layer over the base layer; patterning the anti-fuse layer to form an anti-fuse island; forming an insulating layer over the anti-fuse island; forming a via hole through the insulating layer to the anti-fuse island; forming a conductive connection layer over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.
摘要:
The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
摘要:
An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.
摘要:
Within a dual gate oxide process, gate oxide is formed within regions on a substrate. Gate material, such as polysilicon, is placed over a first region. The gate material extends over field oxide surrounding the first region. Gate oxide within a second region is stripped. The gate material over the first region prevents gate oxide within the first region from being stripped. A new layer of gate oxide is formed within the second region. A first transistor gate is formed within the second region. The gate material which is over the first region is etched to form a second transistor gate.
摘要:
The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.
摘要:
An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug which overlies a layer of a a conductive barrier material such as TiN or TiW that contacts the anti-fuse material and overlies the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separated from the conductive barrier material overlying the anti-fuse layer by the plug. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.
摘要:
Parasitic leakage is minimized in a MOS structure. An integrated circuit wafer comprises conventional MOS elements as applied through a first level metallization. An intermetal dielectric includes three layers, an intermediate organic glass layer used for planarization and upper and lower oxide layers. A second metallization is applied over the dielectric. Passivation includes a lower oxide passivation and an upper nitride passivation. Hydrogen from the nitride passivation migrates into the organic glass and forms positive charges that induce the parasitic leakage. The lower oxide layer in the intermetal dielectric is silicon-enriched to provide dangling bonds which neutralize this charge formation and thus minimize the parasitic leakage.