发明授权
US5199053A Charge transfer device output 失效
充电传输设备输出

  • 专利标题: Charge transfer device output
  • 专利标题(中): 充电传输设备输出
  • 申请号: US911936
    申请日: 1992-07-10
  • 公开(公告)号: US5199053A
    公开(公告)日: 1993-03-30
  • 发明人: Masahide Hirama
  • 申请人: Masahide Hirama
  • 申请人地址: JPX Tokyo
  • 专利权人: Sony Corporation
  • 当前专利权人: Sony Corporation
  • 当前专利权人地址: JPX Tokyo
  • 优先权: JPX3-172633 19910712; JPX3-172634 19910712
  • 主分类号: H01L27/148
  • IPC分类号: H01L27/148 H04N5/335
Charge transfer device output
摘要:
In a CCD element, the influence of a parasitic capacitance existing between a floating diffusion region and a reset gate section of an output section is suppressed to increase sensitivity. In a CCD element in which a floating diffusion region (7) is connected to the final stage of a charge transfer register (1) having a CCD structure through a horizontal output gate section (5) and a reset gate section (11) is disposed between the floating diffusion region (7) and a reset drain region (10), an output gate pulse (.phi..sub.HOG) having an anti-phase of a reset pulse (.phi..sub.RG) applied to the reset gate section (11) is applied to the horizontal output gate section (5). Further, an output waveform in a signal period in a CCD linear sensor can be made flat and a signal level difference between odd-numbered and even-numbered pixels can be improved. In a CCD linear sensor comprising a photo sensing region formed of a plurality of photo sensing elements (pixels), first and second horizontal transfer registers disposed at both sides of the photo sensing region through read-out gate sections, a floating diffusion region for alternately detecting signal charges transferred thereto from the first and second horizontal transfer registers as output signals and a reset gate section, a transfer section of the final stage portion of the first and second horizontal transfer registers is separated and phases of drive pulses (.phi.H.sub.1 '), (.phi.H.sub.2 ') applied to the transfer section of the final stage portion are shifted from those of drive pulses (.phi.H.sub.1), (.phi.H.sub.2) applied to the preceding transfer section, whereby a noise component (36) is superimposed upon the output waveform of ON period (T.sub.R) of the reset gate section.
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