发明授权
US5202969A Single-chip-cache-buffer for selectively writing write-back and
exclusively writing data-block portions to main-memory based upon
indication of bits and bit-strings respectively
失效
单片缓存缓冲器,用于基于位和位串的指示,有选择地写入回写和独占地将数据块部分写入主存储器
- 专利标题: Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively
- 专利标题(中): 单片缓存缓冲器,用于基于位和位串的指示,有选择地写入回写和独占地将数据块部分写入主存储器
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申请号: US871906申请日: 1992-04-21
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公开(公告)号: US5202969A公开(公告)日: 1993-04-13
- 发明人: Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
- 申请人: Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
- 申请人地址: JPX Tokyo JPX Tokyo
- 专利权人: Hitachi, Ltd.,Hitachi VLSI Engineering
- 当前专利权人: Hitachi, Ltd.,Hitachi VLSI Engineering
- 当前专利权人地址: JPX Tokyo JPX Tokyo
- 优先权: JPX63-277624 19881101; JPX63-330040 19881226
- 主分类号: G06F12/08
- IPC分类号: G06F12/08 ; G11C11/4096
摘要:
In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
公开/授权文献
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