公开(公告)号：US06779102B2

公开(公告)日：2004-08-17

申请号：US09886267

申请日：2001-06-22

Applicant: Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

Inventor： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

IPC: G06F1578

CPC classification number: G06F9/30047 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3824 ,  G06F12/0848 ,  G06F12/0891

Abstract: A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.

Abstract translation: 形成在LSI芯片上的数据处理器具有指令地址发生器，指令高速缓冲存储器，其具有各自存储指令地址的条目和与该指令地址对应的指令，指令译码器从对应于指令地址的所述高速缓冲存储器解码指令 所述指令地址生成器，响应于所述指令解码器的输出信号产生操作数地址的操作数地址生成器和具有条目的操作数高速缓存存储器，每个存储操作数地址和对应于其操作数地址的操作数数据。 数据处理器执行使得在所述指令高速缓冲存储器和所述操作数高速缓冲存储器两者中的条目无效的指令。

公开(公告)号：US5253197A

公开(公告)日：1993-10-12

申请号：US580464

申请日：1990-09-11

Applicant: Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi ,  Katsuhiro Shimohigashi ,  Takehisa Hayashi ,  Makoto Hanawa ,  Tadahiko Nishimukai

Inventor： Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi ,  Katsuhiro Shimohigashi ,  Takehisa Hayashi ,  Makoto Hanawa ,  Tadahiko Nishimukai

IPC: G06F12/08 ,  G06F12/10 ,  G11C15/04

CPC classification number: G11C15/04 ,  G06F12/0895 ,  G06F12/1054 ,  Y02B60/1225

Abstract: In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.

Abstract translation: 在本文公开的本发明的CAM（内容可寻址存储器）或高速缓冲存储器的第一实施例中，将存储在存储单元中的比较信息与比较输入信息进行比较，在比较电路中完成，而无需将来自存储单元的读出电流转换成 电压信息。 在另一个实施例中，从第一存储单元阵列输出的第一存储信息与从第二存储单元阵列输出的第二存储信息之间的匹配检测由一体形成的感测和匹配检测电路来实现，其特征在于具有检测和匹配检测 能力 也就是说，感测和匹配检测电路感测存储的信息，并且此后基于感测结果检测匹配。

公开(公告)号：US5202969A

公开(公告)日：1993-04-13

申请号：US871906

申请日：1992-04-21

Applicant: Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

Inventor： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC: G06F12/08 ,  G11C11/4096

CPC classification number: G06F12/0804 ,  G11C11/4096

Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Abstract translation: 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US4942521A

公开(公告)日：1990-07-17

申请号：US119919

申请日：1987-11-13

Applicant: Makoto Hanawa ,  Atsushi Hasegawa ,  Tadahiko Nishimukai

Inventor： Makoto Hanawa ,  Atsushi Hasegawa ,  Tadahiko Nishimukai

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F12/0862

Abstract: When the access is effected sequentially such as the prefetching of an instruction or the restoration of a register in the stack region, the retrieval is effected simultaneously for the consecutive addresses and the result is stored. When the consecutive addresses are to be accessed, the hit is determined relying upon the result that is stored without effecting the cache memory reference. In the case of mishit, the external memory is readily accessed to shorten the overhead time required for the cache memory reference. Therefore, the access time can be shortened in average.

Abstract translation: 当顺序地进行访问，例如预取指令或恢复堆栈区域中的寄存器时，对连续的地址同时进行检索，并且存储结果。 当要访问连续地址时，根据存储的结果确定命中，而不影响缓存存储器引用。 在mishit的情况下，可以容易地访问外部存储器，以缩短高速缓存存储器引用所需的开销时间。 因此，可以平均缩短访问时间。

公开(公告)号：US4937738A

公开(公告)日：1990-06-26

申请号：US768572

申请日：1985-08-23

Applicant: Kunio Uchiyama ,  Atsushi Hasegawa ,  Takeshi Aimoto ,  Tadahiko Nishimukai

Inventor： Kunio Uchiyama ,  Atsushi Hasegawa ,  Takeshi Aimoto ,  Tadahiko Nishimukai

IPC: G06F12/08

CPC classification number: G06F12/0888

Abstract: A cache memory contained in a processor features a high efficiency in spite of its small capacity.In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory.By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.

Abstract translation: 包含在处理器中的高速缓冲存储器具有高效率，尽管其容量小。 在高速缓冲存储器控制电路中，检测处理器的访问操作是否针对存储器的特定区域，并且当数据要被从特定区域读出或被写入时， 数据被复制到高速缓冲存储器上，并且当数据要从其他区域读出时，立即执行存储器的操作而不等待缓存存储器的引用。 通过为要重复使用的数据分配特定区域，可以提供尽管容量小的高效率的高速缓冲存储器。 这种数据的代表性例子是堆栈中的数据。

公开(公告)号：US5740401A

公开(公告)日：1998-04-14

申请号：US9077

申请日：1993-01-26

Applicant: Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

Inventor： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F12/08 ,  G06F12/14 ,  G06F15/177

CPC classification number: G06F9/52 ,  G06F12/0806 ,  G06F12/1466

Abstract: A multiprocessor system includes an address bus 170, a data bus 180, processors 110 and 120, access queues 135 and 145, shared memories 130 and 140, and lock control circuits 500 and 510. Particularly, a lock-in indicative flag register 501 is provided in the lock control circuit 500. While an operand cache 112 in one processor 110 is making a lock access to a predetermined address of the shared memory 130, the flag register 501 is set on the basis of a lock command signal 260 so that an access of an instruction cache 122 in another processor 120 to the predetermined address of the shared memory 130 is prohibited but an access to a different address is permitted at the time of the lock access. After the lock access is released, the lock control circuit 500 accepts an access to the predetermined address.

Abstract translation: 多处理器系统包括地址总线170，数据总线180，处理器110和120，访问队列135和145，共享存储器130和140以及锁定控制电路500和510.特别地，锁定指示标志寄存器501是 当一个处理器110中的操作数高速缓存112正在对共享存储器130的预定地址进行锁定访问时，标志寄存器501是基于锁定命令信号260设置的， 在另一个处理器120中的指令高速缓存122到共享存储器130的预定地址的访问是被禁止的，但是在锁定访问时允许访问不同的地址。 在锁定访问被释放之后，锁定控制电路500接受对预定地址的访问。

公开(公告)号：US5146573A

公开(公告)日：1992-09-08

申请号：US426781

申请日：1989-10-25

Applicant: Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

Inventor： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC: G06F12/08 ,  G11C11/4096

CPC classification number: G11C11/4096 ,  G06F12/0804

Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Abstract translation: 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US4989140A

公开(公告)日：1991-01-29

申请号：US323125

申请日：1989-03-13

Applicant: Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

Inventor： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/345 ,  G06F9/38 ,  G06F9/445 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F13/16 ,  G06F15/78

CPC classification number: G06F9/30047 ,  G06F12/0848 ,  G06F12/0891 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3824

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instruction read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output the instruction to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Abstract translation: 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，该指令控制单元具有从主存储器读出的第一相关存储器存储指令，以及指令控制器，当该指令为指令时，从第一关联存储器读出指令 存在于第一关联存储器中，并且当指令不存在于第一关联存储器中时，指令控制单元产生要执行的指令的输出。 指令执行单元具有第二关联存储器，其存储从主存储器读出的操作数数据，以及指令执行器，当所述操作数数据存在于所述第二关联存储器中时，通过使用从所述第二关联存储器读出的操作数据来执行所述指令; 当操作数数据不存在于第二关联存储器中时，从主存储器。

公开(公告)号：US4803616A

公开(公告)日：1989-02-07

申请号：US781512

申请日：1985-09-30

Applicant: Kunio Uchiyama ,  Tadahiko Nishimukai ,  Atsushi Hasegawa

Inventor： Kunio Uchiyama ,  Tadahiko Nishimukai ,  Atsushi Hasegawa

IPC: G06F12/08 ,  G06F13/00 ,  G06F12/06

CPC classification number: G06F12/0895

Abstract: In a buffer memory, a validity flag to be added to each data portion is stored in a tag array or address section at a location corresponding to each data portion. After determining whether each validity flag is to be used as a search object, based upon the data portion to be accessed during searching the tag array and an access mode, the address and its validity flag are simultaneously searched. The logical sum of each output of the search result on a word coincidence line becomes a hit judgement signal.

Abstract translation: 在缓冲存储器中，要添加到每个数据部分的有效性标志被存储在与每个数据部分相对应的位置处的标签阵列或地址部分中。 在确定是否将每个有效性标志用作搜索对象之后，基于在搜索标签阵列期间要访问的数据部分和访问模式，同时搜索地址及其有效性标志。 字符符号线上的搜索结果的每个输出的逻辑和成为命中判断信号。

公开(公告)号：US6078983A

公开(公告)日：2000-06-20

申请号：US862322

申请日：1997-05-23

Applicant: Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

Inventor： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

IPC: G06F15/16 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/36

CPC classification number: G06F13/1642 ,  G06F13/1605

Abstract: A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, first and second arbiters, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. When a processor requires data from the memory bank, the processor sends a processor ID with a data access request. When the memory bank sends data in return, the memory bank outputs the processor ID of the request originator with the required data. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access requested need not wait for a previous access request to be finished. According, the throughput of the system can be improved greatly. The first and second arbiters serve to decide ownership of buses.

Abstract translation: 本发明的多处理器系统具有地址总线，数据总线，第一和第二处理器，四个访问队列，第一和第二仲裁器以及被划分成四个存储体的共享存储器。 四个访问队列由用于缓冲通过地址总线发送的多个访问请求地址的先进先出存储器构成。 当处理器需要来自存储体的数据时，处理器发送具有数据访问请求的处理器ID。 当存储体返回数据时，存储体输出请求发起者的处理器ID和所需的数据。 即使连续访问请求被寻址到共享存储器的一个组，请求的后续访问也不需要等待先前的访问请求完成。 据说，系统的吞吐量可以大大提高。 第一和第二仲裁者用于决定公共汽车的所有权。