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    SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR
    1.
    发明申请
    SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR 失效
    用于低功率处理器的基板偏置开关单元

    公开(公告)号：US20100005324A1

    公开(公告)日：2010-01-07

    申请号：US12346268

    申请日：2008-12-30

    Applicant: Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    Inventor： Yonetaro TOTSUKA ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    IPC: G06F1/26

    CPC classification number: G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

    Abstract translation: 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

    Processor system using synchronous dynamic memory
    2.
    发明授权
    Processor system using synchronous dynamic memory 失效

    公开(公告)号：US07143230B2

    公开(公告)日：2006-11-28

    申请号：US10752569

    申请日：2004-01-08

    Applicant: Kunio Uchiyama ,  Osamu Nishii

    Inventor： Kunio Uchiyama ,  Osamu Nishii

    IPC: G06F12/00

    CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

    Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

    Data processor and data processor system having multiple modes of address indexing and operation
    6.
    发明授权
    Data processor and data processor system having multiple modes of address indexing and operation 有权
    数据处理器和数据处理器系统具有多种地址索引和操作模式

    公开(公告)号：US06532528B1

    公开(公告)日：2003-03-11

    申请号：US09563753

    申请日：2000-05-01

    Applicant: Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    Inventor： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

    IPC: G06F1210

    CPC classification number: G06F12/1027 ,  G06F2212/652

    Abstract: A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

    Abstract translation: 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

    Semiconductor integrated circuit device
    8.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06436741B2

    公开(公告)日：2002-08-20

    申请号：US09822429

    申请日：2001-04-02

    Applicant: Masayuki Sato ,  Kunio Uchiyama

    Inventor： Masayuki Sato ,  Kunio Uchiyama

    IPC: H01L2100

    CPC classification number: G11C29/12 ,  G11C2029/0401 ,  G11C2029/1206

    Abstract: A logic test having less over-head for testing a logic circuit in a chip is implemented by constituting a test circuit in the chip without introducing a novel device process of FPGA. A memory of a self-configuration type is provided in the chip and a test circuit is constituted in the memory of a self-configuration type or an ordinary memory through a tester HDL, thereby testing other memories and logic circuits in the chip. The test circuit is reconstituted such that the memory used in the structure of the test circuit can be operated as an ordinary memory.

    Abstract translation: 通过在芯片中构成测试电路而不引入FPGA的新颖的器件处理来实现具有用于测试芯片中的逻辑电路的较少过载的逻辑测试。 在芯片中提供自配置型存储器，并且通过测试器HDL在自配置型或普通存储器的存储器中构成测试电路，从而测试芯片中的其他存储器和逻辑电路。 测试电路被重构，使得在测试电路的结构中使用的存储器可以作为普通存储器来操作。

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