The present invention relates to a method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor wherein a polysilicon pad and a polysilicon storage node are simultaneously patterned with a self-alignment method without a mask.Accordingly, the present invention has the following advantages: First, the overlay accuracy can be improved by patterning a polysilicon pad and a polysilicon storage node with a self-alignment method. Second, the fabrication process can be simpler than the prior fabrication process for the semiconductor memory cell of a noble stacked capacitor cell structure. Third, the storage capacitance of a capacitor can be increased.