Invention Grant
- Patent Title: Bus system for information processing system and method of controlling the same
- Patent Title (中): 信息处理系统总线系统及其控制方法
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Application No.: US512810Application Date: 1990-04-20
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Publication No.: US5276818APublication Date: 1994-01-04
- Inventor: Koichi Okazawa , Hiroaki Aotsu , Hitoshi Kawaguchi , Masami Jikihara , Kazushi Kobayashi , Koichi Kimura , Tetsuya Mochida
- Applicant: Koichi Okazawa , Hiroaki Aotsu , Hitoshi Kawaguchi , Masami Jikihara , Kazushi Kobayashi , Koichi Kimura , Tetsuya Mochida
- Applicant Address: JPX Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JPX Tokyo
- Priority: JPX1-101621 19890424; JPX1-332716 19891225
- Main IPC: G06F13/28
- IPC: G06F13/28 ; G06F13/36 ; G06F13/364 ; G06F13/42 ; G06F13/00
Abstract:
A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.
Public/Granted literature
- US4559607A Arrangement to provide an accurate time-of-arrival indication for a plurality of received signals Public/Granted day:1985-12-17
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