A modification to the design of high speed logic circuitry will increase the speed of the circuitry. The modification consists of a delayed negative feedback added to the interface between two gates (a driving gate and a driven gate). The feedback is delayed by a time similar to the gate propagation delay, so that when a transition occurs, the feedback is effectively positive for times less than the feedback delay time. The effect of this is to add a bias at the interface that will aid the next transition of the driven gate during the transition. After a transition, the polarity of the bias is reversed so it will again aid the next transition.