公开(公告)号：US07158062B2

公开(公告)日：2007-01-02

申请号：US10761790

申请日：2004-01-21

申请人： Albert E. Cosand

发明人： Albert E. Cosand

IPC分类号： H03M3/00

CPC分类号： H03M3/376 ,  H03M3/464

摘要： A switch having a first arrangement for providing a first set of first and second complementary intermediate signals; a second arrangement for providing a second set of third and fourth complementary intermediate signals; a third arrangement responsive to the first set of signals for providing complementary output signals; a fourth arrangement responsive to the second set of signals for providing complementary output signals; and a fifth arrangement for selectively activating the third means or the fourth arrangement in response to a control signal.

摘要翻译： 一种开关，具有用于提供第一组第一和第二互补中间信号的第一装置; 用于提供第二组第三和第四互补中间信号的第二装置; 响应于所述第一组信号以提供互补输出信号的第三装置; 响应于所述第二组信号以提供互补输出信号的第四布置; 以及响应于控制信号选择性地激活第三装置或第四装置的第五装置。

公开(公告)号：US5324997A

公开(公告)日：1994-06-28

申请号：US21385

申请日：1993-02-23

申请人： Albert E. Cosand

发明人： Albert E. Cosand

IPC分类号： H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K19/013

摘要： A modification to the design of high speed logic circuitry will increase the speed of the circuitry. The modification consists of a delayed negative feedback added to the interface between two gates (a driving gate and a driven gate). The feedback is delayed by a time similar to the gate propagation delay, so that when a transition occurs, the feedback is effectively positive for times less than the feedback delay time. The effect of this is to add a bias at the interface that will aid the next transition of the driven gate during the transition. After a transition, the polarity of the bias is reversed so it will again aid the next transition.

摘要翻译： 对高速逻辑电路设计的修改将提高电路的速度。 修改包括添加到两个门（驱动门和从动门）之间的接口的延迟负反馈。 反馈被延迟一个类似于门传播延迟的时间，所以当发生转变时，反馈对于小于反馈延迟时间的时间是有效的。 这样做的结果是在界面处增加偏置，这将有助于在转换期间驱动栅极的下一个转换。 在转变之后，偏置的极性反转，因此它将再次帮助下一个转换。

公开(公告)号：US5304951A

公开(公告)日：1994-04-19

申请号：US829183

申请日：1992-01-31

申请人： Albert E. Cosand

发明人： Albert E. Cosand

IPC分类号： H03L7/18 ,  H03L7/189 ,  H03L7/199

CPC分类号： H03L7/199 ,  H03L7/189 ,  H03L2207/18

摘要： A divider synchronization circuit (11) that provides faster settling to a new frequency in a phase-locked loop frequency synthesizer (10) that uses a programmable divider (16) and a phase detector (17). The circuit (11) is adapted to stop the divider (16) while its program is being changed, and then restart the divider (16) on command. The startup time of the divider (16) is automatically adjusted such that the divider output is in phase with a reference input to a phase detector (17). The outputs of the phase detector (17) are also blanked during the time period that the divider (16) is stopped. The circuit (11) reduces the time required for the phase locked-loop frequency synthesizer (10) to settle to its new frequency and phase when the frequency is changed. The timing of the divider startup eliminates the large phase transient that may occur when the divider startup timing is random, thus shortening the time that must be allowed for the synthesizer output to settle to its final phase. This circuit (11) is of particular value in a fast settling synthesizer design in which a VCO is pretuned to a close approximation to the new output frequency and then the loop is closed to drive the frequency to its exact value. The circuit (11) is well adapted for use in spread spectrum and frequency-agile radar systems, or spread spectrum communications systems.

摘要翻译： 一种分频器同步电路（11），其在使用可编程分频器（16）和相位检测器（17）的锁相环频率合成器（10）中提供更快的建立到新的频率。 电路（11）适于在其程序改变时停止分频器（16），然后按命令重新启动分频器（16）。 分频器（16）的启动时间被自动调节，使得分频器输出与与相位检测器（17）的基准输入同相。 在除法器（16）停止的时间段期间，相位检测器（17）的输出也被消隐。 当频率改变时，电路（11）减少锁相环频率合成器（10）在其新的频率和相位上所需的时间。 分频器启动的时序消除了当分频器启动时序是随机时可能发生的大相位瞬变，从而缩短了合成器输出必须允许的时间才能稳定到其最后的相位。 在快速稳定合成器设计中，该电路（11）具有特殊的价值，其中VCO被预先约束到近似于新的输出频率，然后闭环以将频率驱动到其精确值。 电路（11）很好地适用于扩频和频率敏捷雷达系统或扩频通信系统。

公开(公告)号：US07940201B1

公开(公告)日：2011-05-10

申请号：US12497448

申请日：2009-07-02

申请人： Albert E. Cosand

发明人： Albert E. Cosand

IPC分类号： H03M1/00

CPC分类号： H03M1/1255

摘要： An input sampler interface to a track and hold circuit that decouples a high bandwidth (possibly optical domain) input signal from a lower bandwidth electrical domain of a subsequent track and hold circuit or other circuit.

摘要翻译： 与轨道和保持电路的输入采样器接口，其将高带宽（可能的光域）输入信号与随后的跟踪和保持电路或其他电路的较低带宽电域分离。

公开(公告)号：US4975931A

公开(公告)日：1990-12-04

申请号：US286435

申请日：1988-12-19

申请人： Albert E. Cosand

发明人： Albert E. Cosand

IPC分类号： H03K23/64 ,  H03K21/10 ,  H03K23/66 ,  H03K23/68

CPC分类号： H03K23/665 ,  H03K21/10 ,  H03K23/667 ,  H03K23/68

摘要： A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the programmable divider utilizes the multiple clock phases to allow operation in a true fractional-integer mode. The overall combination of the prescaler and programmable divider functions as a programmable divider for which the minimum increment in the overall divider modulus is less than the prescaler modulus, but the maximum clock frequency usable is the maximum clock frequency of the prescaler.

摘要翻译： 可编程计数器或分频器包括固定模数预分频器（110）和可编程分频器（120,130,140,​​150,160）的组合，其中预分频器向可编程分频器提供多于单个时钟相位，并且可编程分频器 分频器利用多个时钟相位允许以真正的分数整数模式运行。 预分频器和可编程分频器的总体组合功能用作可编程分频器，其中总分频器模数的最小增量小于预分频器模数，但可用的最大时钟频率是预分频器的最大时钟频率。

公开(公告)号：US08742965B1

公开(公告)日：2014-06-03

申请号：US13401979

申请日：2012-04-12

申请人： Albert E. Cosand

发明人： Albert E. Cosand

IPC分类号： H03M1/66

CPC分类号： H03M1/68

摘要： Apparatus implementing a monotonic output digital to analog converter (DAC). A high resolution monotonic DAC may be built from a lower resolution DAC using weighting functions that combine the outputs of the lower resolution DAC such that monotonicity is maintained across major carry transitions. The lower resolution DAC should have a true output and a complementary output with a half LSB bias in the output. An extended resolution DAC may be built of; cascaded low resolution DACs; a low resolution DAC in a recursive arrangement with an intermediate storage of its output; or a low resolution DAC with weighting functions that adjust at each of several major carry transition.

摘要翻译： 实现单调输出数模转换器（DAC）的装置。 高分辨率单调DAC可以使用组合低分辨率DAC的输出的加权函数从较低分辨率DAC构建，使得在主要进位转变之间保持单调性。 较低分辨率DAC应具有真实的输出和输出中半LSB偏置的互补输出。 扩展分辨率DAC可以构建; 级联低分辨率DAC; 低分辨率DAC，其递归排列与其输出的中间存储; 或具有加权功能的低分辨率DAC，可在几个主要进位转换中进行调整。

公开(公告)号：US07701375B1

公开(公告)日：2010-04-20

申请号：US12261828

申请日：2008-10-30

申请人： Albert E. Cosand

发明人： Albert E. Cosand

IPC分类号： H03M1/12

CPC分类号： H03M7/165 ,  H03M1/0809 ,  H03M1/361

摘要： An encoder for encoding comparator outputs of a bank of 2**N−1 comparators into an N bit binary code is provided. The comparator outputs have redundancy so that if comparator output Cw is a binary zero, then each comparator output numbered Cx wherein x is greater than w, is binary zero, and if comparator output Cy is binary one, then each comparator output numbered Cz wherein z is less than y, is binary one. The encoder for encoding an Mth bit of the N bit binary code includes N−M+1 levels of current steering switches. The Lth level has 2**(L−1) current steering switches each connected to a current steering switch in an (L−1)th level, except when the Lth level is 1. The comparator outputs are connected to the current steering switches.

摘要翻译： 提供了一种编码器，用于将2 ** N-1比较器组的比较器输出编码为N位二进制码。 比较器输出具有冗余，因此如果比较器输出Cw为二进制零，则编号为Cx的每个比较器输出，其中x大于w，为二进制零，如果比较器输出Cy为二进制，则每个比较器输出编号为Cz，其中z 小于y，是二进制的。 用于编码N位二进制码的第M位的编码器包括当前转向开关的N-M + 1电平。 L级具有两个**（L-1）个电流转向开关，各自连接到（L-1）级的电流转向开关，除了当第L级为1时。比较器输出连接到当前转向开关 。

公开(公告)号：US07573305B1

公开(公告)日：2009-08-11

申请号：US12041085

申请日：2008-03-03

申请人： Albert E. Cosand ,  Susan Morton

发明人： Albert E. Cosand ,  Susan Morton

IPC分类号： H03B19/00

CPC分类号： H03K23/542

摘要： A high speed divider circuit is disclosed. The circuit contains a plurality of latches and buffers. The maximum input clock frequency of the divider circuit is increased over that implemented with only latches connected in a ring by feed forwarding the output of an early switching latch to the output of a later switching latch through buffers. The feed forward signal aids the later switching latch to complete the next state transition. By choosing the appropriate ratio of the buffer tail current to the latch tail current, the divider circuit can be made into a dynamic divider circuit.

摘要翻译： 公开了一种高速分频器电路。 电路包含多个锁存器和缓冲器。 分频器电路的最大输入时钟频率比通过将早期切换锁存器的输出通过缓冲器向稍后的切换锁存器的输出进给馈送而连接在环中的锁存器实现的增加。 前馈信号有助于稍后的切换锁存器完成下一个状态转换。 通过选择缓冲尾电流与闭锁电流的适当比例，分频电路可以制成动态分频电路。

公开(公告)号：US06999019B2

公开(公告)日：2006-02-14

申请号：US10821376

申请日：2004-04-08

申请人： Albert E. Cosand

发明人： Albert E. Cosand

IPC分类号： H03M1/12 ,  H03M1/00

CPC分类号： H03M1/145

摘要： A subranging analog-to-digital converter (ADC) includes an integrating sample-and-hold circuit. The integrating sample-and-hold circuit is configured to sample an input voltage by charging at least one capacitor by coupling a current proportional to the input voltage to the at least one capacitor. A coarsely-quantizing ADC is configured to convert the voltage on the at least one capacitor to a digitized value. A digital-to-analog converter is configured to convert the digitized value to an analog voltage. A finely-quantizing ADC is configured to convert the difference between the analog voltage and the voltage on the charged at least one capacitor in the integrating sample-and-hold circuit to another digitized value.

摘要翻译： 子阵列模数转换器（ADC）包括积分采样保持电路。 集成采样和保持电路被配置为通过将与输入电压成比例的电流耦合到至少一个电容器来对至少一个电容器进行充电来对输入电压进行采样。 粗量化ADC被配置为将至少一个电容器上的电压转换为数字化值。 数模转换器被配置为将数字化值转换为模拟电压。 精细量化的ADC被配置为将积分采样保持电路中充电的至少一个电容器上的模拟电压和电压之间的差转换成另一数字化值。

公开(公告)号：US06975682B2

公开(公告)日：2005-12-13

申请号：US09879470

申请日：2001-06-12

申请人： Albert E. Cosand

发明人： Albert E. Cosand

IPC分类号： H03M3/04 ,  H04B14/06

CPC分类号： H03M3/338 ,  H03M3/424

摘要： A quantizer adapted for use with a delta-sigma analog-to-digital converter. The quantizer includes first and second comparators adapted to compare an input analog signal to a threshold and provide a digital output in response thereto. First and second thresholds are provided to the first and second comparators respectively. In accordance with the present teachings, a mechanism is provided for changing the thresholds to minimize conversion errors. While the mechanism for changing the thresholds may be implemented with resistive and/or capacitive ladders, in the illustrative embodiment, digital-to-analog converters are utilized. The DACs are driven by error shaping logic. The inventive quantizer allows for an improved delta-sigma analog-to-digital converter design which combines an ADC and a DAC. The DAC reconstructs the analog equivalent of the digital output of the ADC. The ADC is a flash converter consisting of one comparator per threshold. The DAC operates by summing the outputs of a set of nominally identical unit elements. The DAC has the same number of elements as there are comparators in the flash ADC and each comparator drives one element of the DAC. A novel feature is that the thresholds of the comparators in the ADC can individually be dynamically adjusted, so that the correspondence between an element of the DAC and a particular threshold of the ADC can be varied from sample to sample under the control of logic circuitry. This arrangement allows the correspondence between DAC elements and ADC thresholds to be remapped without introducing any additional delay into the signal path between the ADC and the DAC. In a high speed continuous-time delta sigma modulator, this allows randomization or shaping of the mismatch errors of the DAC elements to be achieved without incurring any penalty in sample rate, nor adding any excess delay into the loop that might destabilize or otherwise degrade the operation of the modulator.