A CMOS gate circuit constituting the input stage of a semiconductor logic circuit includes a p channel MOS transistor supplied with current from a first power supply potential Vdd for charging an output signal line to a high level potential, a diode provided between MOS transistor and output signal line, an n channel MOS transistor supplied with current from a second power supply potential Vss responsive to an input signal (Vin) for discharging the potential of output signal line, and a diode provided between MOS transistor and output signal line. An input signal potential applied to input stage has its logic amplitude set to be Vdd-Vf to Vf. Vf represents the forward voltage of the diodes and the second power supply potential is set to be ground potential GND. The input signal potential has its logic amplitude limited, current flows through the diodes in its steady state, and, therefore, the logic amplitude of the signal potential Vout of output signal line becomes Vdd-Vf to Vf.