发明授权
US5384741A Semiconductor memory device adapted for preventing a test mode operation
from undesirably occurring
失效
适于防止测试模式操作不期望地发生的半导体存储器件
- 专利标题： Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring
- 专利标题（中）： 适于防止测试模式操作不期望地发生的半导体存储器件
-
申请号： US186955申请日： 1994-01-27
-
公开(公告)号： US5384741A公开(公告)日： 1995-01-24
- 发明人: Yoshiyuki Haraguchi , Yutaka Arita
- 申请人： Yoshiyuki Haraguchi , Yutaka Arita
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX4-166475 19920625
- 主分类号： G01R31/28
- IPC分类号： G01R31/28 ; G11C11/401 ; G11C11/413 ; G11C29/00 ; G11C29/14 ; G11C29/46 ; H01L21/66 ; H01L27/10
摘要：
A semiconductor memory device having a circuit for preventing the operation of a test mode includes a first terminal for receiving an externally applied high voltage exceeding a power supply potential, a second terminal for receiving an externally applied test mode signal and a high voltage detector for detecting that a high voltage signal has been applied through the first terminal. A test mode signal holding circuit is responsive to the high voltage detector and holds the test mode signal applied through the second terminal. A test circuit is responsive to the test mode signal held in the test mode signal holding circuit and performs a test in the semiconductor memory device. A disabling circuit is provided to disable the high voltage detector.
公开/授权文献
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