A write address counter for designating a write address of a memory counts up a control counter with an address change. A read address counter for designating a read address of the memory counts down the control counter with the address change. Inputted to an error detecting circuit are a write address counter value, a read address counter value and a control count value. There is detected whether a relationship such as Write Address Count Value-Read Address Count Value=Control Count Value is established or not. If not established, this implies an error, and a reset circuit resets each counter.