发明授权
- 专利标题： Method DRAM polycide rowline formation
- 专利标题（中）： 方法DRAM多晶硅行线形成
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申请号： US67660申请日： 1993-05-26
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公开(公告)号： US5425392A公开(公告)日： 1995-06-20
- 发明人: Randhir P. S. Thakur , Fernando Gonzalez , Annette L. Martin
- 申请人： Randhir P. S. Thakur , Fernando Gonzalez , Annette L. Martin
- 申请人地址： ID Boise
- 专利权人： Micron Semiconductor, Inc.
- 当前专利权人： Micron Semiconductor, Inc.
- 当前专利权人地址： ID Boise
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L21/8239
摘要：
The present invention teaches a method for reducing sheet resistance in the fabrication of semiconductor wafers. A silicon substrate having a gate oxide layer thereon is provided in a chamber. Subsequently, a polysilicon layer is formed superjacent the gate oxide layer in situ by exposing the silicon substrate to a first gas comprising at least one of silane, disilane, and dichlorosilane, and radiant energy at a temperature substantially within the range of 500.degree. C. to 1250.degree. C. for at least 10 seconds. The polysilicon substrate can be doped with a material such as phosphorus, arsenic and boron for example, by exposing the polysilicon to a second gas under the stated conditions. A conductive layer comprising at least one of tungsten silicide (WSi.sub.x) and titanium silicide (TiSi.sub.x) can be formed superjacent the polysilicon by exposing the polysilicon to a third gas comprising at least one of WF.sub.6, TMAT and TiCl.sub.4.
公开/授权文献
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