Invention Grant
US5475250A Matrix of EPROM memory cells with a tablecloth structure having an
improved capacitive ratio and a process for its manufacture
失效
具有具有改进的电容比的桌布结构的EPROM存储器单元的矩阵及其制造方法
- Patent Title: Matrix of EPROM memory cells with a tablecloth structure having an improved capacitive ratio and a process for its manufacture
- Patent Title (中): 具有具有改进的电容比的桌布结构的EPROM存储器单元的矩阵及其制造方法
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Application No.: US191667Application Date: 1994-02-04
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Publication No.: US5475250APublication Date: 1995-12-12
- Inventor: Orio Bellezza
- Applicant: Orio Bellezza
- Applicant Address: ITX Agrate Brianza
- Assignee: SGS-Thomson Microelectronics S.r.l.
- Current Assignee: SGS-Thomson Microelectronics S.r.l.
- Current Assignee Address: ITX Agrate Brianza
- Priority: ITX22848/88 19881205
- Main IPC: H01L21/8247
- IPC: H01L21/8247 ; H01L27/115 ; H01L29/68
Abstract:
The matrix of EPROM memory cells comprises on a semiconductor substrate lines of source and drain parallel and alternated one to another, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas. Field oxide areas are provided for, formed on the substrate between one and the other of said control gate lines and side fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.
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