公开(公告)号：US5723351A

公开(公告)日：1998-03-03

申请号：US521469

申请日：1995-08-30

Applicant: Orio Bellezza

Inventor： Orio Bellezza

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S257/90

Abstract: The matrix of EPROM memory cells comprises on a semiconductor substrate lines of source and drain parallel and alternated one to another, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate area. Field oxide areas are provided for, formed on the substrate between one and the other of said control gate lines and side fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.

Abstract translation: EPROM存储单元的矩阵包括在源极和漏极平行并交替的半导体衬底上，彼此交替布置在所述源极和漏极线之间的棋盘图案中的浮动栅极区域和彼此平行并垂直于所述源极的控制栅极线 和漏极线，其叠加状态具有中间介质并且相对于所述浮动栅极区对准。 提供场氧化物区域，用于形成在衬底上的所述控制栅极线和浮栅区域的侧鳍之间以及叠加在所述场氧化物区域上的控制栅极线的侧鳍之间。

公开(公告)号：US5296396A

公开(公告)日：1994-03-22

申请号：US929418

申请日：1992-08-14

Applicant: Orio Bellezza

Inventor： Orio Bellezza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/70

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S257/90

Abstract: The matrix of EPROM memory cells comprises on a semiconductor substrate lines of source and drain parallel and alternated one to another, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas. Field oxide areas are provided for, formed on the substrate between one and the other of said control gate lines and side fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.

Abstract translation: EPROM存储单元的矩阵包括在源极和漏极平行并交替的半导体衬底上，彼此交替布置在所述源极和漏极线之间的棋盘图案中的浮动栅极区域和彼此平行并垂直于所述源极的控制栅极线 以及具有中间电介质并且相对于所述浮动栅区对准的叠加状态的漏极线。 提供场氧化物区域，用于形成在衬底上的所述控制栅极线和浮栅区域的侧鳍之间以及叠加在所述场氧化物区域上的控制栅极线的侧鳍之间。

公开(公告)号：US5475250A

公开(公告)日：1995-12-12

申请号：US191667

申请日：1994-02-04

Applicant: Orio Bellezza

Inventor： Orio Bellezza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/68

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S257/90

Abstract: The matrix of EPROM memory cells comprises on a semiconductor substrate lines of source and drain parallel and alternated one to another, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas. Field oxide areas are provided for, formed on the substrate between one and the other of said control gate lines and side fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.

Abstract translation: EPROM存储单元的矩阵包括在源极和漏极平行并交替的半导体衬底上，彼此交替布置在所述源极和漏极线之间的棋盘图案中的浮动栅极区域和彼此平行并垂直于所述源极的控制栅极线 以及具有中间电介质并且相对于所述浮动栅区对准的叠加状态的漏极线。 提供场氧化物区域，用于形成在衬底上的所述控制栅极线和浮栅区域的侧鳍之间以及叠加在所述场氧化物区域上的控制栅极线的侧鳍之间。

公开(公告)号：US5117269A

公开(公告)日：1992-05-26

申请号：US487480

申请日：1990-03-02

Applicant: Orio Bellezza ,  Massimo Melanotte

Inventor： Orio Bellezza ,  Massimo Melanotte

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11517 ,  H01L27/115

Abstract: In order to obtain an EPROM memory array with high compactness and the possibility of asymmetrically doping the channel, an array is proposed which comprises a substrate having a first conductivity type, first and second bit lines having the opposite conductivity type and extending parallel and mutually alternated in the substrate, a plurality of thick insulating material regions extending at least partially in the substrate above and parallel to the first bit lines, a plurality of floating gate regions extending above the substrate perpendicular to and between adjacent pairs of bit lines, a plurality of word lines extending perpendicular to the bit lines and above, but electrically insulated from, the floating gate regions, wherein the second bit lines extend up to the surface of the substrate and define unburied bit lines to the side whereof it is possible to provide enriched channel regions. The unburied bit lines can furthermore be subjected to a siliciding process to reduce series resistance.

公开(公告)号：US5723350A

公开(公告)日：1998-03-03

申请号：US70084

申请日：1993-05-28

Applicant: Gabriella Fontana ,  Orio Bellezza ,  Giuseppe Paolo Crisenza

Inventor： Gabriella Fontana ,  Orio Bellezza ,  Giuseppe Paolo Crisenza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: An improved fabrication process employing relatively non-critical masks permits the fabrication of high density electrically programmable and erasable EEPROM or FLASH-EPROM devices. In practice the novel process permits the fabrication of a contactless, cross-point array providing for a more comfortable "pitch" of bitline metal-definition while realizing a cell layout with a gate structure which extends laterally over adjacent portions of field oxide, thus establishing an appropriate capacitive coupling between control and floating gates. Two alternative embodiments are described.

公开(公告)号：US5707884A

公开(公告)日：1998-01-13

申请号：US458059

申请日：1995-06-01

Applicant: Gabriella Fontana ,  Orio Bellezza ,  Giuseppe Paolo Crisenza

Inventor： Gabriella Fontana ,  Orio Bellezza ,  Giuseppe Paolo Crisenza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: An improved fabrication process employing relatively non-critical masks permits the fabrication of high density electrically programmable and erasable EEPROM or FLASH-EPROM devices. In practice the novel process permits the fabrication of a contactless, cross-point array providing for a more comfortable "pitch" of bitline metal-definition while realizing a cell layout with a gate structure which extends laterally over adjacent portions of field oxide, thus establishing an appropriate capacitive coupling between control and floating gates. Two alternative embodiments are described.

Abstract translation: 使用相对非关键掩模的改进的制造工艺允许制造高密度电可编程和可擦除EEPROM或FLASH-EPROM器件。 实际上，新颖的工艺允许制造非接触的交叉点阵列，以提供更舒适的位线金属清晰度的“间距”，同时实现具有在场氧化物的相邻部分上横向延伸的栅极结构的电池布局，从而建立 控制和浮动门之间的适当电容耦合。 描述两个备选实施例。

公开(公告)号：US5160986A

公开(公告)日：1992-11-03

申请号：US759203

申请日：1991-09-11

Applicant: Orio Bellezza

Inventor： Orio Bellezza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The matrix of EPROM memory cells comprises on a semiconductor substrate lines of source and drain parallel and alternated one to another, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas. Field oxide areas are provided for, formed on the substrate between one and the other of said control gate lines and side fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.

Abstract translation: EPROM存储单元的矩阵包括在源极和漏极平行并交替的半导体衬底上，彼此交替布置在所述源极和漏极线之间的棋盘图案中的浮动栅极区域和彼此平行并垂直于所述源极的控制栅极线 以及具有中间电介质并且相对于所述浮动栅区对准的叠加状态的漏极线。 提供场氧化物区域，用于形成在衬底上的所述控制栅极线和浮栅区域的侧鳍之间以及叠加在所述场氧化物区域上的控制栅极线的侧鳍之间。

公开(公告)号：US5063424A

公开(公告)日：1991-11-05

申请号：US503931

申请日：1990-04-04

Applicant: Massimo Melanotte ,  Orio Bellezza

Inventor： Massimo Melanotte ,  Orio Bellezza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11517 ,  H01L27/115

Abstract: The UPROM memory cell comprises self-aligned lines of source and lines of drain obtained in a semiconductor substrate. It also comprises a strip of floating gate, a strip of dielectric and a strip of barrier polysilicon, each of these strips being provided with a respective pair of small lateral fins. The UPROM cell lastly comprises a control gate superimposed over and self-aligned with the floating gate.