发明授权
- 专利标题： Method for forming a linear heterojunction field effect transistor
- 专利标题（中）： 用于形成线性异质结场效应晶体管的方法
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申请号： US229266申请日： 1994-04-18
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公开(公告)号： US5482875A公开(公告)日： 1996-01-09
- 发明人: Rimantas L. Vaitkus , Saied N. Tehrani , Vijay K. Nair , Herbert Goronkin
- 申请人： Rimantas L. Vaitkus , Saied N. Tehrani , Vijay K. Nair , Herbert Goronkin
- 申请人地址： IL Schaumburg
- 专利权人： Motorola, Inc.
- 当前专利权人： Motorola, Inc.
- 当前专利权人地址： IL Schaumburg
- 主分类号： H01L29/812
- IPC分类号： H01L29/812 ; H01L21/338 ; H01L29/08 ; H01L29/10 ; H01L29/778 ; H01L29/80 ; H01L21/335
摘要：
A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.
公开/授权文献
- US4890596A Arrow rest 公开/授权日：1990-01-02
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