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公开(公告)号：US5943574A
公开(公告)日：1999-08-24
申请号：US27915
申请日：1998-02-23
IPC分类号： H01L21/336 , H01L21/768 , H01L27/06 , H01L27/092 , H01L29/786
CPC分类号： H01L29/6675 , H01L21/76838 , H01L27/0688 , H01L27/0922 , H01L29/78642
摘要： A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.
摘要翻译： 一种制造3D半导体电路的方法，包括向其上形成有导电层的掺杂多晶硅进行图案化和退火，以形成半导体器件的第一单晶多晶硅端子。 绝缘栅极触点与端子垂直间隔开，以便限定垂直通孔，并且多孔沉积在通孔中以形成传导通道。 通孔中的多晶硅的上部被掺杂以形成用于半导体器件的第二端子，并且将多晶硅退火以将其转换成单晶粒多晶硅。 在第二端子上沉积和图案化第二导电层以限定半导体器件的第二端子触点。
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2.发明授权Method of selecting a memory cell in a magnetic random access memory device 失效选择磁性随机存取存储器件中的存储单元的方法
公开(公告)号：US5748519A
公开(公告)日：1998-05-05
申请号：US766637
申请日：1996-12-13
申请人： Saied N. Tehrani , Herbert Goronkin
发明人： Saied N. Tehrani , Herbert Goronkin
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L21/78
CPC分类号： G11C11/15
摘要： Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided. Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected. This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed. Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell.
摘要翻译： 提供了用于选择磁随机存取存储器（MRAM）中的存储单元的改进方法。 每当检测到存储单元中的状态时，MRAM需要在检测到存储器单元的内容之前将比较器的输出调整为零电压（自动调零步骤）。 一旦感测线25被选择并自动归零，本发明顺序地访问存储器单元29-30。 因此，由于本发明不需要每次感测存储单元的自动归零步骤，所以实现了更高的速度操作。
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3.发明授权
公开(公告)号：US5659179A
公开(公告)日：1997-08-19
申请号：US399809
申请日：1995-03-07
IPC分类号： H01L29/06 , H01L21/329 , H01L27/06 , H01L29/88
CPC分类号： H01L29/66219 , H01L27/0605 , H01L29/882
摘要： Ultra-small semiconductor devices and a method of fabrication including patterning the planar surface of a substrate to form a pattern edge (e.g. a mesa) and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edge so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.
摘要翻译： 超小型半导体器件和制造方法包括图案化衬底的平坦表面以形成图案边缘（例如台面）并且以与图案边缘重叠的关系连续地形成多个半导体材料层，使得不连续性为 在图案边缘的一侧上产生的层和第一层与图案边缘的另一侧上的不同层对准并与之接触。
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公开(公告)号：US5591666A
公开(公告)日：1997-01-07
申请号：US511776
申请日：1995-08-07
IPC分类号： H01L21/205 , H01L21/20 , H01L29/88
CPC分类号： H01L21/02395 , H01L21/02546 , H01L21/0262 , H01L21/02639 , Y10S117/902 , Y10S117/913 , Y10S438/973
摘要： A method of fabricating semiconductor devices including defining an area on the surface of a substrate, selectively growing, on the area, a crystalline material with at least one defined crystallographic facet, and selectively growing a semiconductor device on the crystallographic facet. In a second embodiment, an area is defined on the surface of a substrate and chemical beam epitaxy is used to selectively grow, on the area, a layer of indium arsenide with at least one defined crystallographic facet.
摘要翻译： 一种制造半导体器件的方法，包括限定衬底的表面上的区域，在该区域上选择性地生长具有至少一个限定的结晶小面的晶体材料，以及在晶面上选择性地生长半导体器件。 在第二实施例中，在衬底的表面上限定一个区域，并且使用化学束外延在该区域上选择性地在至少一个限定的晶面上生长砷化铟层。
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公开(公告)号：US5326985A
公开(公告)日：1994-07-05
申请号：US951994
申请日：1992-09-28
申请人： Herbert Goronkin , Jun Shen , Saied N. Tehrani
发明人： Herbert Goronkin , Jun Shen , Saied N. Tehrani
IPC分类号： H01L29/778 , H01L29/161 , H01L29/205
CPC分类号： H01L29/7783
摘要： A semiconductor structure that provides both N-type and P-type doping from a single dopant source is provided. A first doping region (13) comprising a first material composition includes holes and electrons in a doping energy level (E.sub.D)- A first undoped spacer region (12) comprising the first material composition covers the doping region (13). An undoped channel (11,14) comprising a second material composition covers the first spacer region (12) and a second undoped spacer region (12) comprising the first material composition covers the undoped channel (11,14). The first material composition has a wider bandgap than the second material composition and the doping energy level (E.sub.D) is selected to provide electrons to the undoped channel (11,14) when the second material composition has a conduction band minimum less than the doping energy level (E.sub.D) and to provide holes to the first undoped channel (11,14) when the second material composition has a valence band maximum greater than the doping energy level (E.sub.D).
摘要翻译： 提供了从单个掺杂剂源提供N型和P型掺杂的半导体结构。 包括第一材料组合物的第一掺杂区域（13）包括掺杂能级（ED）的空穴和电子 - 包含第一材料组合物的第一未掺杂间隔区域（12）覆盖掺杂区域（13）。 包括第二材料组合物的未掺杂通道（11,14）覆盖第一间隔区域（12），并且包括第一材料组合物的第二未掺杂间隔区域（12）覆盖未掺杂沟道（11,14）。 第一材料组合物具有比第二材料组成更宽的带隙，并且当第二材料组合物具有小于掺杂能量的导带最小值时，选择掺杂能级（ED）以向未掺杂沟道（11,14）提供电子 （ED），并且当第二材料组合物具有大于掺杂能级（ED）的价带最大值时，向第一未掺杂通道（11,14）提供孔。
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公开(公告)号：US5289013A
公开(公告)日：1994-02-22
申请号：US769659
申请日：1991-10-02
申请人： Herbert Goronkin
发明人： Herbert Goronkin
CPC分类号： B82Y10/00 , H01L29/122
摘要： A quantum well structure having a host optical phonon confinement well (11) having a characteristic phonon distribution (16), and at least one charge carrier confinement well (17) located near a minima of the phonon distribution (16). In one embodiment, a wide bandgap layer (13) is formed in a central portion of the host optical phonon confinement well (11), wherein the wide bandgap layer (13) has phonon properties closely matching that of the host phonon confinement well (11).
摘要翻译： 具有具有特征声子分布（16）的主光学声子限制阱（11）和位于声子分布（16）的最小值附近的至少一个电荷载流子限制阱（17）的量子阱结构。 在一个实施例中，在主光学声子限制阱（11）的中心部分中形成宽带隙层（13），其中宽带隙层（13）具有与主机声子限制孔（11）的声子特性密切相关的声子特性 ）。
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公开(公告)号：US5286982A
公开(公告)日：1994-02-15
申请号：US796285
申请日：1991-11-22
IPC分类号： G02F1/015 , G02F1/017 , H01L27/12 , H01L27/14 , H01L29/161
摘要： A thin transition layer (13) is employed to provide alignment between an electron wave function (29) and a hole wave function (37) of an optical modulator (10) for a wide range of applied voltage values that are less than a predetermined value. Over this range of voltages, the modulator (10) is in an off state and substantially absorbs incident light (19). For applied voltages in excess of the predetermined value, the electron (29) and hole wave (37) function alignment is diminished thereby allowing light (19) to be transmitted through the modulator (10).
摘要翻译： 使用薄过渡层（13）来提供小于预定值的宽范围的施加电压值的光调制器（10）的电子波函数（29）和空穴波函数（37）之间的对准 。 在该电压范围内，调制器（10）处于关闭状态并且基本上吸收入射光（19）。 对于超过预定值的施加电压，电子（29）和空穴波（37）的功能对准被减小，从而允许光（19）通过调制器（10）传输。
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8.发明授权Self-doped high performance complementary heterojunction field effect transistor 失效自掺杂高性能互补异质结场效应晶体管
公开(公告)号：US5142349A
公开(公告)日：1992-08-25
申请号：US724077
申请日：1991-07-01
IPC分类号： H01L21/338 , H01L21/8238 , H01L27/06 , H01L27/092 , H01L27/095 , H01L29/10 , H01L29/20 , H01L29/778 , H01L29/80 , H01L29/812
CPC分类号： H01L27/0605 , H01L27/0922 , H01L29/1029 , H01L29/802
摘要： A heterojunction field effect transistor structure having a plurality of vertically stacked field effect devices. Two or more devices having electrically independent source and drain regions are formed such that a single gate electrode controls current flow in each of the devices. Each of the vertically stacked FETs have electrically isolated channel regions which may be controlled by a single gate electrode. Vertically stacked devices provide greater device packing density.
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9.发明授权
公开(公告)号：US5081511A
公开(公告)日：1992-01-14
申请号：US578167
申请日：1990-09-06
申请人： Saied N. Tehrani , Herbert Goronkin
发明人： Saied N. Tehrani , Herbert Goronkin
IPC分类号： H01L29/812 , H01L21/335 , H01L21/338 , H01L29/12 , H01L29/36 , H01L29/43 , H01L29/778
CPC分类号： B82Y10/00 , H01L29/122 , H01L29/432 , H01L29/66462 , H01L29/7783 , H01L29/365
摘要： A heterojunction field effect transistor (HFET) having a source, drain, and channel, wherein the channel comprises a quantum well and at least one mono-atomic well or barrier layer is provided. The mono-atomic well or barrier layer has a different bandgap than the channel region and serves to modify electron wave function and conduction band energy in the channel region. Preferably, an indium arsenide well monolayer is formed in an InGaAs channel region and functions to move a first quantized energy level E.sub.0 closer to the bottom of the channel region quantum well thereby increasing electron concentration by increasing effective band offset potential. Another embodiment uses an aluminum arsenide monolayer as a barrier monolayer in the InGaAs channel. By varying location of the monolayers, confinement of electrons in the channel can be improved.
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10.发明授权Magnetic random access memory having stacked memory cells and fabrication method therefor 失效具有堆叠存储单元的磁性随机存取存储器及其制造方法
公开(公告)号：US5920500A
公开(公告)日：1999-07-06
申请号：US702781
申请日：1996-08-23
IPC分类号： G11C11/15 , G11C11/14 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L43/08
CPC分类号： G11C11/14 , H01L27/222
摘要： A magnetic random access memory (10) has a plurality of stacked memory cells on semiconductor substrate (11), each cell basically having a portion of magnetic material (12), a word line (13), and sense line (14). Upper sense line (22) is electrically coupled to lower sense line (12) via conductor line (23) with ohmic contacts. In order to read and store states in the memory cell, lower and upper word lines (13, 18) are activated, thereby total magnetic field is applied to portion of magnetic material (11). This stacked memory structure allows magnetic random access memory (10) to integrate more memory cells on semiconductor substrate (11).
摘要翻译： 磁性随机存取存储器（10）在半导体衬底（11）上具有多个堆叠的存储单元，每个单元基本上具有一部分磁性材料（12），字线（13）和感测线（14）。 上感测线（22）经由导体线（23）与欧姆接触电耦合到下感测线（12）。 为了读取和存储存储单元中的状态，上下文字线（13,18）被激活，从而将总磁场施加到磁性材料（11）的一部分。 这种堆叠式存储器结构允许磁性随机存取存储器（10）将更多的存储器单元集成在半导体衬底（11）上。
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