For correction of an error caused in a period of a clock signal for digitizing a plurality of time signals, e.g., from an image sensor, a clock signal generating device generates a reference signal Sr indicative of a reference time of time signals TS from an OR-date (20). The device counts a reference clock signal .phi. in a frequency divider (30) until the reference signal Sr is generated, and outputs a divided clock signal .phi..sub.n with frequency dividing ratio 1/N from the frequency divider (30). It then counts the signal .phi..sub.n and stores the count value as a reference value S in a reference value counter (40). The device outputs an output clock signal .phi..sub.o from an output counter (50) each time the signal .phi. received after generation of the signal Sr reaches a predetermined value. It accumulates in an accumulator (60) the count value of the frequency divider (30) at the time of generation of the signal Sr in response to the signal .phi..sub.o, and it sets a reference value of the counter (50) for counting the signal .phi., to generate the signal .phi..sub.o usually at S, and at 1+S when an accumulated value in the accumulator (60) reaches the parameter N of the frequency dividing ratio.