In order to thin an input signal a second multiplexer is switched to output an output of a first adder and a third multiplexer is switched to output an output of a second adder, and a first multiplexer is alternatively switched at every line. A delay circuit memorizes the sum of the two preceding input signals, and the second adder outputs at every other line the sum of image data of a present line and the two preceding lines. To interpolate an input signal, the second multiplexer is switched to output the output of the delay circuit, the first multiplexer is alternatively switched to output either the input signal or the output of the second multiplexer, and the second multiplexer is alternatively switched to output either the output of the first adder or the output of the delay circuit. Thus, the delay circuit outputs at every other line the sum of the two preceding input signals. Because only one delay circuit is needed the size of the perpendicular thinning/interpolation circuit for an image signal is reduced.