Abstract:
Provided is a frame rate conversion apparatus for inputting a video signal and inserting an interpolation frame into the video signal so as to convert a frame rate of the video signal. The apparatus includes: an input unit for inputting the video signal; a video interpolation unit for generating an interpolation frame and performing an interpolation process of the video signal; and a control unit for controlling the generation process of the interpolation frame by the video interpolation unit. The video interpolation unit performs the interpolation frame generation process by using a plurality of methods, and the control unit controls switching between the plurality of interpolation frame generating methods.
Abstract:
A method for transforming an original image to a new image is provided. The original image includes M rows of original data; the new image includes Q rows of new data. The method first generates a (2i−1)th row and a (2i)th row of intermediate data respectively based on the (2i−1)th row and the (2i)th row of original data. Then, the method generates a (2i+1)th row and a (2i+2)th row of intermediate data respectively based on the (2i+1)th row and the (2i+2)th row of original data. During the process of generating the (2i+1)th row of intermediate data, the (2j−1)th row of new data is simultaneously generated based on the (2i−1)th row and the (2i+1)th row of intermediate data. During the process of generating the (2i+2)th row of intermediate data, the (2j)th row of new data is simultaneously generated based on the (2i)th row and the (2i+2)th row of intermediate data.
Abstract:
A digital signal converting method and device for converting an input image rate into an output image rate, is applied to input images which are formed by a plurality of input data frames. The method storing the input frames, calculating a sliding average over a plurality of stored frames, and deriving the averages for producing output images with a timing fixed by the output image rate.
Abstract:
A vertical compression circuit of an image playback system displaying an image through interlaced scanning includes: a mode counter for counting horizontal lines within one section of vertical lines based on a compression mode signal and outputting a count; a coefficient selection signal generating unit for outputting a coefficient selection signal for selecting first and second filtering coefficients and for outputting a feedback control signal, based on the compression mode signal; a first coefficient selecting unit for generating first coefficients corresponding to various compression modes and outputting one of the first coefficients based on the first coefficient selection signal; a second coefficient selecting unit for generating second coefficients corresponding to various compression modes and outputting one of the second coefficients based on the second coefficient selection signal; an adder for adding the second coefficient output from the second coefficient selecting unit to one of zero and a feedback value, based on the feedback signal to produce a sum; a line memory unit for storing the output from the adder, wherein the adder outputs the second coefficient output from the second coefficient selecting unit if the feedback signal indicates no feedback, and the adder outputs the sum of the second coefficient output from the second coefficient selecting unit and a value previously stored in the line memory if the feedback signal indicates feedback; and a unit for adding the contents of the line memory unit and the output of the first coefficient selecting unit, and outputting a result.
Abstract:
An apparatus and method for improving the display of progressively scanned images on displays that employ an interlace display technique. The apparatus comprises a vertical filter and a clipper. An input image is vertically low-pass and high-pass filtered through the vertical filter. The resulting high-pass signal is passed through the clipper such that a non-linear transfer function limits the maximum value that is permitted to pass through the clipper. The "clipped" high-pass signal is then recombined with the low-pass signal to reconstruct a flicker-reduced image. In this fashion, interline flicker is reduced while maintaining the full resolution of natural images.
Abstract:
A memory device for a digital video system, capable of receiving video data in a packed format and transmitting that video data in a planar format. In other operating modes, the memory device receives video data in various packed formats and transmits that video data in a packed format. The memory device is suitable for a flexible digital video system in which video data may either be displayed in real time as it is generated (using packed format data) or compressed for storage and future display (using planar format data).
Abstract:
A circuit for producing a chroma signal which includes both of a first and a second color difference signal on each of scanning lines in response to a line-sequential color difference signal in which a first and a second color difference signal appear alternately on consecutive scanning lines. A carrier generator generates a first and a second color subcarrier which are different in phase from each other in synchronism with the line-sequential color difference signal. The first color subcarrier is subjected to balanced modulation at a first modulator which uses the first color difference signal for the modulation while the second color subcarrier is subjected to balanced modulation at a second modulator which uses the second color difference signal. The outputs of the first and second modulators are added together by a first adder. A delay circuit is provided for delaying an output of the first adder by a period of time which is substantially equal to one horizontal scanning period. The output of the delay circuit is added to the output of the first adder by a second adder to produce the chroma signal. The circuit eliminates the need for operations heretofore performed for bringing color difference signals into coincidence at the baseband and thereby the need for delay circuits, switching circuits and adjusting circuits which implement such operations.
Abstract:
A signal separator performs an inter-line operation on a composite color video signal, thereby separating it into a luminance signal and a chrominance signal. A scan converter converts each of the luminance signal and the chrominance signal into a sequential scan signal on the basis of the double-speed changing of the luminance signal and the chrominance signal. A signal determination circuit determines whether the composite color video signal is a standard signal or a non-standard signal. A first clock producer produces first clocks to be phase-locked to a color subcarrier in accordance with the composite color digital video signal. A second clock producer produces second clocks to be phase-locked to horizontal synchronizing signals in accordance with the composite color digital video signal. A first controller causes the signal separator and the scan converter to operate in accordance with the first clocks when the signal determination circuit determines that the signal is a standard signal. A second controller causes the signal separator to operate in accordance with the first clocks, causes the scan converter to operate in accordance with the second clocks, and converts a sampling rate of each of the luminance signal and the chrominance signal separated by the signal separator in accordance with the first clock into a rate of the second clocks when the signal determination circuit determines that the signal is a non-standard signal.
Abstract:
An apparatus interpolates color-difference line-sequential signals appearing alternately in a video signal together with a luminance signal. The video signal is received by an input circuit and then held temporarily and on a horizontal scanning line basis by a hold circuit. Each of the color-difference signals is interpolated by an interpolating circuit by producing an arithmetic mean of the color-difference data of the video signal being held by the hold circuit and color-difference data of the video signal being received by the input circuit, on the basis of the pixels corresponding to each other on horizontal scanning lines.
Abstract:
A clamping circuit for use in a line sequential video processor sets separate dc voltage levels for a pair of color difference signals. The respective dc levels serve to identify the sequence of the color difference signals in the line sequential signal. By first setting the voltage offset between the respective levels, the dc voltage levels for both color difference signals are later established by clamping only to every other signal. The clamping circuit includes a monostable multivibrator that generates a clamping pulse only at the onset of every other color difference signal.