发明授权
- 专利标题: Flash memory control method and information processing system therewith
- 专利标题(中): 闪存控制方法和信息处理系统
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申请号: US225313申请日: 1994-04-08
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公开(公告)号: US5530673A公开(公告)日: 1996-06-25
- 发明人: Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
- 申请人: Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
- 申请人地址: JPX Tokyo JPX Chiba-ken JPX Tokyo
- 专利权人: Hitachi, Ltd.,Hitachi Keiyo Engineering Co., Ltd.,Hitachi ULSI Engineering Corp.
- 当前专利权人: Hitachi, Ltd.,Hitachi Keiyo Engineering Co., Ltd.,Hitachi ULSI Engineering Corp.
- 当前专利权人地址: JPX Tokyo JPX Chiba-ken JPX Tokyo
- 优先权: JPX5-081642 19930408; JPX5-122401 19930525; JPX5-174372 19930714; JPX5-175619 19930715; JPX5-246520 19931001
- 主分类号: G06F3/06
- IPC分类号: G06F3/06 ; G06F11/14 ; G06F12/08 ; G11C29/00 ; G11C16/06 ; G06F12/16
摘要:
A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.
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