Invention Grant
- Patent Title: Identification of pin-open faults by capacitive coupling through the integrated circuit package
- Patent Title (中): 通过集成电路封装的电容耦合识别引脚开路故障
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Application No.: US400787Application Date: 1995-03-07
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Publication No.: US5557209APublication Date: 1996-09-17
- Inventor: David T. Crook , Kevin W. Keirn , Ugur Cilingiroglu
- Applicant: David T. Crook , Kevin W. Keirn , Ugur Cilingiroglu
- Applicant Address: CA Palo Alto
- Assignee: Hewlett-Packard Company
- Current Assignee: Hewlett-Packard Company
- Current Assignee Address: CA Palo Alto
- Main IPC: G01R31/04
- IPC: G01R31/04 ; G01R31/312 ; G01R31/02
Abstract:
Disclosed is a system that determines whether input and output pins of semiconductor components are present and properly soldered to a printed circuit board. The system uses an oscillator which supplies a signal, typically ten kilohertz (10 kHz) at 0.2 volts, to the pin under test. A conductive electrode is placed on top of the component package. The electrode is connected to a current measuring device. Another pin of the component is connected to the common signal return. Typically the other pin is chosen to be a power or ground pin of the component.
Public/Granted literature
- US4996250A Water-dilutable air-drying protective coating compositions Public/Granted day:1991-02-26
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