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6 条记录 (耗时 0.034 秒)

    Identification of pin-open faults by capacitive coupling through the integrated circuit package
    1.
    发明授权
    Identification of pin-open faults by capacitive coupling through the integrated circuit package 失效
    通过集成电路封装的电容耦合识别引脚开路故障

    公开(公告)号：US5557209A

    公开(公告)日：1996-09-17

    申请号：US400787

    申请日：1995-03-07

    申请人： David T. Crook ,  Kevin W. Keirn ,  Ugur Cilingiroglu

    发明人： David T. Crook ,  Kevin W. Keirn ,  Ugur Cilingiroglu

    IPC分类号： G01R31/04 ,  G01R31/312 ,  G01R31/02

    CPC分类号： G01R31/048 ,  G01R31/046 ,  G01R31/312

    摘要： Disclosed is a system that determines whether input and output pins of semiconductor components are present and properly soldered to a printed circuit board. The system uses an oscillator which supplies a signal, typically ten kilohertz (10 kHz) at 0.2 volts, to the pin under test. A conductive electrode is placed on top of the component package. The electrode is connected to a current measuring device. Another pin of the component is connected to the common signal return. Typically the other pin is chosen to be a power or ground pin of the component.

    摘要翻译： 公开了一种确定半导体部件的输入和输出引脚是否存在并被适当地焊接到印刷电路板的系统。 该系统使用一个振荡器，该信号通常以0.2伏特的十千赫兹（10 kHz）信号提供给被测试的引脚。 导电电极放置在组件封装的顶部。 电极连接到电流测量装置。 组件的另一个引脚连接到公共信号返回。 通常，另一个引脚被选择为部件的电源或接地引脚。

    Identification of pin-open faults by capacitive coupling
    4.
    发明授权
    Identification of pin-open faults by capacitive coupling 失效
    通过电容耦合识别引脚开路故障

    公开(公告)号：US5696451A

    公开(公告)日：1997-12-09

    申请号：US848909

    申请日：1992-03-10

    申请人： Kevin W. Keirn ,  David T. Crook

    发明人： Kevin W. Keirn ,  David T. Crook

    IPC分类号： G01R31/02 ,  G01R31/04 ,  G01R31/28 ,  G01R31/312 ,  G01R27/26

    CPC分类号： G01R31/04 ,  G01R31/312

    摘要： Disclosed is a system that determines whether input and output pins of semiconductor components are present and properly soldered to a circuit assembly. The system includes an oscillator which is connected to a probe that is brought into contact with a circuit assembly wiring trace soldered to the pin being tested. A conductive electrode is placed on top of the component and connected to a capacitance measuring circuit. The oscillator signal is capacitively coupled through the integrated circuit package to the pin being tested, so if capacitance is measured by the capacitance measuring device, the pin is connected to the circuit assembly. An amplifier may be connected to the conductive electrode to amplify the signal, and a segmented probe may be used to isolate individual pins. The probe may be shielded, and unused pins may be grounded.

    摘要翻译： 公开了一种确定半导体部件的输入和输出引脚是否存在并被适当地焊接到电路组件的系统。 该系统包括连接到探针的振荡器，该探针与焊接到被测试引脚上的电路组件布线迹线相接触。 将导电电极放置在部件的顶部并连接到电容测量电路。 振荡器信号通过集成电路封装电容耦合到被测试的引脚，因此如果电容由电容测量装置测量，则该引脚连接到电路组件。 可以将放大器连接到导电电极以放大信号，并且可以使用分段探针来隔离各个引脚。 探头可能被屏蔽，未使用的引脚可能接地。

    Method for compressing data-vectors for a circuit board testing machine
    5.
    发明授权
    Method for compressing data-vectors for a circuit board testing machine 失效
    用于压缩电路板测试机的数据矢量的方法

    公开(公告)号：US5001418A

    公开(公告)日：1991-03-19

    申请号：US449362

    申请日：1989-12-06

    申请人： Kenneth E. Posse ,  Kevin W. Keirn ,  Michael A. Lassner ,  George L. Booth

    发明人： Kenneth E. Posse ,  Kevin W. Keirn ,  Michael A. Lassner ,  George L. Booth

    IPC分类号： G06F11/277 ,  G06T9/00 ,  H03M7/30

    CPC分类号： G06T9/008 ,  G06F11/277 ,  H03M7/30

    摘要： Disclosed is a method for compressing sequences of data-vectors, which sequences are to be used for testing circuit boards with the aid of a circuit board testing machine. The method involves an initial compression of the data-vector sequence followed by a so-called K-T transformation of the remaining data-vectors. The initial compression involves eliminating redundant data-vectors from the initial sequence and retaining only the unique data-vectors together with sequencing information indicating where in the initial sequence each unique-data vector occurred. The K-T transformation involves a bitwise logical exclusive-OR operation (XOR) whereby the remaining data-vector sequence is K-T transformed thereby further compressing the sequence without losing any of the original sequence information.

    摘要翻译： 公开了一种用于压缩数据矢量序列的方法，该方法借助于电路板测试机将用于测试电路板。 该方法涉及数据向量序列的初始压缩，随后是剩余数据向量的所谓的K-T变换。 初始压缩包括从初始序列中消除冗余数据向量，并且仅保留唯一的数据向量以及指示在初始序列中每个唯一数据向量发生的位置的排序信息。 K-T变换涉及按位逻辑异或运算（XOR），由此剩余的数据矢量序列被K-T变换，从而进一步压缩序列而不损失任何原始序列信息。

    Integrated circuit transfer test device system utilizing lateral transistors
    6.
    发明授权
    Integrated circuit transfer test device system utilizing lateral transistors 失效
    集成电路传输测试设备系统利用横向晶体管

    公开(公告)号：US5101152A

    公开(公告)日：1992-03-31

    申请号：US472926

    申请日：1990-01-31

    申请人： Vance R. Harwood ,  Kevin W. Keirn ,  John J. Keller ,  Ronald J. Peiffer

    发明人： Vance R. Harwood ,  Kevin W. Keirn ,  John J. Keller ,  Ronald J. Peiffer

    IPC分类号： G01R31/02 ,  G01R31/28

    CPC分类号： G01R31/2813

    摘要： Disclosed is a system for determining whether semiconductor components are present and properly connected to a printed circuit board. The semi-conductor material between two pins of an integrated circuit forms a lateral NPN transistor, having its base connected directly to the substrate connection pin of the component. A constant voltage source is applied to the lateral transistor collector pin of the component being tested, and allowed to stabilize. A current or voltage source is then connected to the emitter pin of the lateral transistor, typically an adjacent pin, and a current or voltage pulse is applied to this pin. The current on the collector pin is then monitored and if a corresponding current pulse is detected, the emitter and collector pins, as well as the substrate connection pin of the component, are properly connected to the printed circuit board.