发明授权
US5565792A Macrocell with product-term cascade and improved flip flop utilization
失效
宏单元,具有产品级级联和改进的触发器利用率
- 专利标题: Macrocell with product-term cascade and improved flip flop utilization
- 专利标题(中): 宏单元,具有产品级级联和改进的触发器利用率
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申请号: US301504申请日: 1994-09-06
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公开(公告)号: US5565792A公开(公告)日: 1996-10-15
- 发明人: David Chiang , Napoleon W. Lee , Thomas Y. Ho , David A. Harrison , Nicholas Kucharewski, Jr. , Jeffrey H. Seltzer
- 申请人: David Chiang , Napoleon W. Lee , Thomas Y. Ho , David A. Harrison , Nicholas Kucharewski, Jr. , Jeffrey H. Seltzer
- 申请人地址: CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: CA San Jose
- 主分类号: H03K19/173
- IPC分类号: H03K19/173 ; H03K3/037 ; H03K19/177
摘要:
A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.
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