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    Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization
    1.
    发明授权
    Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization 失效
    具有增加的速度和改善的触发器利用率的多路复用的旁路存储器件

    公开(公告)号：US5570051A

    公开(公告)日：1996-10-29

    申请号：US454908

    申请日：1995-05-31

    申请人： David Chiang ,  Napoleon W. Lee ,  Thomas Y. Ho ,  Nicholas Kucharewski, Jr.

    发明人： David Chiang ,  Napoleon W. Lee ,  Thomas Y. Ho ,  Nicholas Kucharewski, Jr.

    IPC分类号： H03K19/173 ,  H03K3/037 ,  H03K19/177 ,  H03K3/289

    CPC分类号： H03K19/17732 ,  H03K19/17704

    摘要： A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.

    摘要翻译： 可以通过使用多路复用时钟和高效的器件设计和增强的触发器利用来实现具有增加的存储速度和增强的存储器利用率的存储器件。 可以通过多路复用的时钟信号来控制通过电路的传输时间，从而可以控制电路速度，并通过在信号路径中使用更少的晶体管来增加数据，并通过旁路触发器的主器件将数据直接传输到触发器输出 锁存输入。

    Cross point interconnect structure with reduced area
    2.
    发明授权
    Cross point interconnect structure with reduced area 失效
    交叉点互连结构，减少面积

    公开(公告)号：US5530378A

    公开(公告)日：1996-06-25

    申请号：US430207

    申请日：1995-04-26

    申请人： Nicholas Kucharewski, Jr. ,  David Chiang ,  Jesse H. Jenkins, IV

    发明人： Nicholas Kucharewski, Jr. ,  David Chiang ,  Jesse H. Jenkins, IV

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/1737

    摘要： An erasable programmable logic device (EPLD) includes function blocks connected by a universal interconnect matrix (UIM). The UIM includes both a cross-point circuit and a multiplexer-based (MUX-based) circuit. The cross-point circuit includes intersecting first and second conductors programmably connected by memory cells having control gates connected to the first conductors, drains connected to the second conductors, and sources connected to ground. The MUX-based circuit includes third and fourth conductors programmably connected by pass-gates having first terminals connected to the third conductors, second terminals connected to the fourth conductors, and gates connected to memory cells. The UIM further includes multiple-input multiplexers having first input lines connected to the cross-point circuit, second input lines connected to the MUX-based circuit, and output lines connected to the input lines of the function blocks. The multiple-input multiplexers are programmable to selectively apply signals from either the cross-point circuit or the MUX-based circuit to the function block input lines.

    摘要翻译： 可擦除可编程逻辑器件（EPLD）包括通过通用互连矩阵（UIM）连接的功能块。 UIM包括交叉点电路和基于多路复用器（MUX）的电路。 交叉点电路包括可编程地由具有连接到第一导体的控制栅极，连接到第二导体的漏极和连接到地的源的存储器单元可编程地连接的相交的第一和第二导体。 基于MUX的电路包括可编程地由通过栅极连接的第三和第四导体，其具有连接到第三导体的第一端子，连接到第四导体的第二端子和连接到存储器单元的栅极。 UIM还包括具有连接到交叉点电路的第一输入线，连接到基于MUX的电路的第二输入线和连接到功能块的输入线的输出线的多输入多路复用器。 多输入多路复用器是可编程的，以选择性地将来自交叉点电路或基于MUX的电路的信号应用于功能块输入线。

    Circuit for partially reprogramming an operational programmable logic device
    6.
    发明授权
    Circuit for partially reprogramming an operational programmable logic device 失效
    用于部分重新编程操作可编程逻辑器件的电路

    公开(公告)号：US5764076A

    公开(公告)日：1998-06-09

    申请号：US670472

    申请日：1996-06-26

    申请人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

    发明人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

    IPC分类号： G06F17/50 ,  H03K19/177

    CPC分类号： H03K19/17752 ,  G06F17/5054 ,  H03K19/17704 ,  H03K19/17756

    摘要： A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

    摘要翻译： 一种复杂的可编程逻辑器件（PLD），包括多个可编程功能块和用于接收编程指令的指令总线。 编程指令用于对功能块进行编程，以使PLD能够执行一个或多个所需的逻辑功能。 PLD还包括连接到每个功能块的指令阻塞电路。 当用户指示时，指令分块电路有选择地阻止来自一个或多个功能块的指令总线上的编程指令，同时允许其他功能块接收编程指令。 因此，PLD中的一个或多个功能块被重新编程，而不中断剩余功能块的操作。

    Sense circuit with selectable zero power single input function mode
    7.
    发明授权
    Sense circuit with selectable zero power single input function mode 失效
    感应电路采用可选零功率单输入功能模式

    公开(公告)号：US5506523A

    公开(公告)日：1996-04-09

    申请号：US204717

    申请日：1994-03-01

    申请人： David Chiang ,  Nicholas Kucharewski, Jr.

    发明人： David Chiang ,  Nicholas Kucharewski, Jr.

    IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C16/28 ,  H03K19/00 ,  G11C7/00

    CPC分类号： H03K19/0016 ,  G11C16/0441 ,  G11C16/26 ,  G11C16/28

    摘要： The present invention provides a sense circuit including a first bit line, a second bit line, a first plurality of memory cells coupled to the first bit line, a second plurality of memory cells coupled to the second bit line, and selection circuitry coupled to the first bit line and the second bit line. The selection circuitry provides a wide AND gate function in one mode and provides a zero power circuit for generating a function of a single input in another mode.

    摘要翻译： 本发明提供了一种感测电路，其包括第一位线，第二位线，耦合到第一位线的第一多个存储器单元，耦合到第二位线的第二多个存储单元，以及耦合到第二位线的选择电路 第一位线和第二位线。 选择电路在一种模式下提供宽的与门功能，并且提供用于在另一模式中产生单个输入的功能的零功率电路。