A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.3 are connected to a first memory-cell-selection line, the first conductive layer L.sub.1 and the third conductive layer L.sub.3 are connected to a second memory-cell-selection line, the second conductive layer L.sub.2 is connected to a fixed potential, and the semiconductor channel forming region Ch.sub.2 is connected to a read/write selection line.