发明授权
US5613083A Translation lookaside buffer that is non-blocking in response to a miss
for use within a microprocessor capable of processing speculative
instructions
失效
翻译后备缓冲区是响应于在能够处理推测性指令的微处理器内使用的错误而非阻塞的
- 专利标题: Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions
- 专利标题(中): 翻译后备缓冲区是响应于在能够处理推测性指令的微处理器内使用的错误而非阻塞的
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申请号: US316089申请日: 1994-09-30
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公开(公告)号: US5613083A公开(公告)日: 1997-03-18
- 发明人: Andrew F. Glew , Haitham Akkary , Glenn J. Hinton
- 申请人: Andrew F. Glew , Haitham Akkary , Glenn J. Hinton
- 申请人地址: CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G06F12/10
- IPC分类号: G06F12/10
摘要:
A translation lookaside buffer is described for use with a microprocessor capable of speculative and out-of-order processing of memory instructions. The translation lookaside buffer is non-blocking in response to translation lookaside buffer misses requiring page table walks. Once a translation lookaside buffer miss is detected, a page table walk is initiated to satisfy the miss. During the page table walk, additional memory instructions are processed by the translation lookaside buffer. Any additional instructions which cause translation lookaside buffer hits are merely processed by the translation lookaside buffer. However, instructions causing translation lookaside buffer misses while the page table walk is being performed are blocked pending completion of the page table walk. Once the page table walk is completed the blocked instructions are reawakened and are again processed by the translation lookaside buffer. Global and selective wakeup mechanisms are described. An implementation wherein the non-blocking translation lookaside buffer is provided within a microprocessor capable of speculative and out-of-order processing is also described.
公开/授权文献
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