发明授权
US5634119A Computer processing unit employing a separate millicode branch history
table
失效
计算机处理单元采用单独的millicode分支历史表
- 专利标题: Computer processing unit employing a separate millicode branch history table
- 专利标题(中): 计算机处理单元采用单独的millicode分支历史表
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申请号: US369441申请日: 1995-01-06
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公开(公告)号: US5634119A公开(公告)日: 1997-05-27
- 发明人: Philip G. Emma , Joshua W. Knight, III , Thomas R. Puzak , James R. Robinson , A. James Van Norstrand, Jr.
- 申请人: Philip G. Emma , Joshua W. Knight, III , Thomas R. Puzak , James R. Robinson , A. James Van Norstrand, Jr.
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: G06F9/318
- IPC分类号: G06F9/318 ; G06F9/38 ; G06F9/32
摘要:
A computer processing system includes a first memory that stores instructions belonging to a first instruction set architecture and a second memory that stores instructions belonging to a second instruction set architecture. An instruction buffer is coupled to the first and second memories, for storing instructions that are executed by a processor unit. The system operates in one of two modes. In a first mode, instructions are fetched from the first memory into the instruction buffer according to data stored in a first branch history table. In the second mode, instructions are fetched from the second memory into the instruction buffer according to data stored in a second branch history table.The first instruction set architecture may be system level instructions and the second instruction set architecture may be millicode instructions that, for example, define a complex system level instruction and/or emulate a third instruction set architecture.
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