发明授权
- 专利标题: Semiconductor integrated circuit having logi gates
- 专利标题(中): 具有逻辑门的半导体集成电路
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申请号: US608605申请日: 1996-02-29
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公开(公告)号: US5675548A公开(公告)日: 1997-10-07
- 发明人: Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
- 申请人: Yuji Yokoyama , Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yutaka Kobayashi , Tatsumi Yamauchi , Shigeru Takahashi , Nobuyuki Gotou , Akira Ide
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX2-010946 19900120; JPX2-046717 19900227
- 主分类号: G11C7/10
- IPC分类号: G11C7/10 ; G11C8/10 ; H03K19/0948 ; G11C8/00
摘要:
An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
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