A test system is provided which tests the on chip cache of a microprocessor (CPU). The test system provides test vectors to the CPU in a specified sequences. The CPU then uses its internal general purpose registers to write the vectors the cache memory locations. After writing, the data is read back and compared to an expected value. The results are then stored in other general purpose registers of the CPU. Using the CPUs general purpose registers to record the test results allows the test system to test many cache locations in parallel. Furthermore the test system allows the test to proceed in a fixed number of CPU clock cycles regardless of any detected errors.