发明授权
US5721927A Method for verifying contiquity of a binary translated block of
instructions by attaching a compare and/or branch instruction to
predecessor block of instructions
失效
用于通过将比较和/或分支指令附加到先前的指令块来验证二进制翻译的指令块的持续性的方法
- 专利标题： Method for verifying contiquity of a binary translated block of instructions by attaching a compare and/or branch instruction to predecessor block of instructions
- 专利标题（中）： 用于通过将比较和/或分支指令附加到先前的指令块来验证二进制翻译的指令块的持续性的方法
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申请号： US689357申请日： 1996-08-07
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公开(公告)号： US5721927A公开(公告)日： 1998-02-24
- 发明人: Leonid Baraz , Yaron Farber
- 申请人： Leonid Baraz , Yaron Farber
- 申请人地址： CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： G06F9/318
- IPC分类号： G06F9/318 ; G06F9/38 ; G06F9/45 ; G06F9/455 ; G06F11/28 ; G06F9/32
摘要：
A method for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions in an order of execution. The method includes appending a compare instruction to the first block of instructions. The compare instruction compares a first value from the first block of instructions with a second value from the second block of instructions, which precedes the first block of instructions in the order of execution. The method further includes appending a branching instruction to the first block of instructions. The branching instruction is executed in response to the first value being unequal to the second value. The branching instruction, when executed, branches to an alternative look-up routine to obtain a block of instructions that follows the second block of instructions in the order of execution.
公开/授权文献
- US5102495A Method providing multiple-processing of substrates 公开/授权日：1992-04-07
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