发明授权
US5742190A Method and apparatus for clocking latches in a system having both pulse
latches and two-phase latches
失效
用于在具有脉冲锁存器和两相锁存器的系统中对锁存器计时的方法和装置
- 专利标题: Method and apparatus for clocking latches in a system having both pulse latches and two-phase latches
- 专利标题(中): 用于在具有脉冲锁存器和两相锁存器的系统中对锁存器计时的方法和装置
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申请号: US670486申请日: 1996-06-27
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公开(公告)号: US5742190A公开(公告)日: 1998-04-21
- 发明人: Jashojiban Banik , Keng L. Wong
- 申请人: Jashojiban Banik , Keng L. Wong
- 申请人地址: CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G06F1/10
- IPC分类号: G06F1/10 ; H03K3/037 ; H03K5/15 ; H03L7/00
摘要:
A method and apparatus for clocking latches in a system having both pulse latches and two-phase latches includes a clock generating circuit for generating a local clock signal based on a global clock signal and also includes a pulse generating circuit for generating a pulse signal based on the global clock signal. A clock signal path transfers the local clock signal from the clock generating circuit to both a first portion and a second portion of the two-phase latch. Similarly, a pulse signal path transfers the pulse signal from the pulse generating circuit to the pulse latch. According to one embodiment, the pulse generating circuit and the clock generating circuit have paths of equal delay, thereby causing a rising edge of the local clock signal to occur at the same time as a rising edge of the pulse signal.
公开/授权文献
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